Diseño de circuitos de columna para memoria SRAM para su integración en un microprocesador con arquitectura RISCV

Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2018.This document describes the design of the periphery circuits for 64 word of 32 bits SRAM memory, specifically for the write driver and sensing amplifier. Technology used was 180nm CMOS. All designs and simulations were deployed in Custom Compiler tool from Synopsys. Every circuit model considered on this work has been compared to each other, in order to determine which one suits better memory requirements. As comparison result, best option was chosen as per space and power consumption criteria has emerged and peripherals layout was designed to be included on memory layout design. Finally, SRAM memory with reading/writing capacity over all its positions, at 20 MHz clock and 1.8V power supply, was implemented

A Design-for-Diagnosis Technique for SRAM Write Drivers

International audienceDiagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information of fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core-cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost Design-for-Diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512x512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of write drivers (logic and analog levels on bit lines)