Intelligent optimization of Circuit placement on FPGA

Field programmable gate arrays (FPGAs) have revolutionized the way digital systems are designed and built over the past decade. With architectures capable of holding tens of millions of logic gates on the horizon and planned integration of configurable logic into system-on-chip platforms, the versatility of programmable devices expected to increase dramatically. Placement is one of the vital steps in mapping a design into FPGA in order to take best advantage of the resources and flexibility provided by it. Here, we propose to test techniques of Placement Optimization on MCNC Benchmark circuits. PSO (Particle Swarm Optimization) has been implemented on circuit netlist with bounding box as cost function. Alternate cost functions were also employed to verify efficiency of optimization. Furthermore, lazy descent was introduced into the algorithm to impede premature convergence. Different values of acceleration and weighing factors were used in the implementation and corresponding convergence results were analyzed. Keywords- FPGA Placement; Particle Swarm Optimization; MCNC Benchmarks Circuits; Bounding Box driven Placement

A CONGESTION DRIVEN PLACEMENT ALGORITHM FOR FPGA SYNTHESIS

We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method [1] used in the state-of-the-art FPGA place and route package VPR [2], our algorithm achieves channel width reduction on 70 % of the 20 largest MCNC benchmark circuits (10.1 % on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced. 1