1,795 research outputs found
PyCARL: A PyNN Interface for Hardware-Software Co-Simulation of Spiking Neural Network
We present PyCARL, a PyNN-based common Python programming interface for
hardware-software co-simulation of spiking neural network (SNN). Through
PyCARL, we make the following two key contributions. First, we provide an
interface of PyNN to CARLsim, a computationally-efficient, GPU-accelerated and
biophysically-detailed SNN simulator. PyCARL facilitates joint development of
machine learning models and code sharing between CARLsim and PyNN users,
promoting an integrated and larger neuromorphic community. Second, we integrate
cycle-accurate models of state-of-the-art neuromorphic hardware such as
TrueNorth, Loihi, and DynapSE in PyCARL, to accurately model hardware latencies
that delay spikes between communicating neurons and degrade performance. PyCARL
allows users to analyze and optimize the performance difference between
software-only simulation and hardware-software co-simulation of their machine
learning models. We show that system designers can also use PyCARL to perform
design-space exploration early in the product development stage, facilitating
faster time-to-deployment of neuromorphic products. We evaluate the memory
usage and simulation time of PyCARL using functionality tests, synthetic SNNs,
and realistic applications. Our results demonstrate that for large SNNs, PyCARL
does not lead to any significant overhead compared to CARLsim. We also use
PyCARL to analyze these SNNs for a state-of-the-art neuromorphic hardware and
demonstrate a significant performance deviation from software-only simulations.
PyCARL allows to evaluate and minimize such differences early during model
development.Comment: 10 pages, 25 figures. Accepted for publication at International Joint
Conference on Neural Networks (IJCNN) 202
An On-chip Trainable and Clock-less Spiking Neural Network with 1R Memristive Synapses
Spiking neural networks (SNNs) are being explored in an attempt to mimic
brain's capability to learn and recognize at low power. Crossbar architecture
with highly scalable Resistive RAM or RRAM array serving as synaptic weights
and neuronal drivers in the periphery is an attractive option for SNN.
Recognition (akin to reading the synaptic weight) requires small amplitude bias
applied across the RRAM to minimize conductance change. Learning (akin to
writing or updating the synaptic weight) requires large amplitude bias pulses
to produce a conductance change. The contradictory bias amplitude requirement
to perform reading and writing simultaneously and asynchronously, akin to
biology, is a major challenge. Solutions suggested in the literature rely on
time-division-multiplexing of read and write operations based on clocks, or
approximations ignoring the reading when coincidental with writing. In this
work, we overcome this challenge and present a clock-less approach wherein
reading and writing are performed in different frequency domains. This enables
learning and recognition simultaneously on an SNN. We validate our scheme in
SPICE circuit simulator by translating a two-layered feed-forward Iris
classifying SNN to demonstrate software-equivalent performance. The system
performance is not adversely affected by a voltage dependence of conductance in
realistic RRAMs, despite departing from linearity. Overall, our approach
enables direct implementation of biological SNN algorithms in hardware
Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Network
We have calculated the key characteristics of associative
(content-addressable) spatial-temporal memories based on neuromorphic networks
with restricted connectivity - "CrossNets". Such networks may be naturally
implemented in nanoelectronic hardware using hybrid CMOS/memristor circuits,
which may feature extremely high energy efficiency, approaching that of
biological cortical circuits, at much higher operation speed. Our numerical
simulations, in some cases confirmed by analytical calculations, have shown
that the characteristics depend substantially on the method of information
recording into the memory. Of the four methods we have explored, two look
especially promising - one based on the quadratic programming, and the other
one being a specific discrete version of the gradient descent. The latter
method provides a slightly lower memory capacity (at the same fidelity) then
the former one, but it allows local recording, which may be more readily
implemented in nanoelectronic hardware. Most importantly, at the synchronous
retrieval, both methods provide a capacity higher than that of the well-known
Ternary Content-Addressable Memories with the same number of nonvolatile memory
cells (e.g., memristors), though the input noise immunity of the CrossNet
memories is somewhat lower
Design Space Exploration and Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays: Device-Circuit Non-Idealities and System Accuracy
In-memory computing (IMC) utilizing synaptic crossbar arrays is promising for
deep neural networks to attain high energy efficiency and integration density.
Towards that end, various CMOS and post-CMOS technologies have been explored as
promising synaptic device candidates which include SRAM, ReRAM, FeFET,
SOT-MRAM, etc. However, each of these technologies has its own pros and cons,
which need to be comparatively evaluated in the context of synaptic array
designs. For a fair comparison, such an analysis must carefully optimize each
technology, specifically for synaptic crossbar design accounting for device and
circuit non-idealities in crossbar arrays such as variations, wire resistance,
driver/sink resistance, etc. In this work, we perform a comprehensive design
space exploration and comparative evaluation of different technologies at 7nm
technology node for synaptic crossbar arrays, in the context of IMC robustness
and system accuracy. Firstly, we integrate different technologies into a
cross-layer simulation flow based on physics-based models of synaptic devices
and interconnects. Secondly, we optimize both technology-agnostic design knobs
such as input encoding and ON-resistance as well as technology-specific design
parameters including ferroelectric thickness in FeFET and MgO thickness in
SOT-MRAM. Our optimization methodology accounts for the implications of device-
and circuit-level non-idealities on the system-level accuracy for each
technology. Finally, based on the optimized designs, we obtain inference
results for ResNet-20 on CIFAR-10 dataset and show that FeFET-based crossbar
arrays achieve the highest accuracy due to their compactness, low leakage and
high ON/OFF current ratio
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