A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Adversarial Semi-Supervised Audio Source Separation applied to Singing Voice Extraction

The state of the art in music source separation employs neural networks trained in a supervised fashion on multi-track databases to estimate the sources from a given mixture. With only few datasets available, often extensive data augmentation is used to combat overfitting. Mixing random tracks, however, can even reduce separation performance as instruments in real music are strongly correlated. The key concept in our approach is that source estimates of an optimal separator should be indistinguishable from real source signals. Based on this idea, we drive the separator towards outputs deemed as realistic by discriminator networks that are trained to tell apart real from separator samples. This way, we can also use unpaired source and mixture recordings without the drawbacks of creating unrealistic music mixtures. Our framework is widely applicable as it does not assume a specific network architecture or number of sources. To our knowledge, this is the first adoption of adversarial training for music source separation. In a prototype experiment for singing voice separation, separation performance increases with our approach compared to purely supervised training.Comment: 5 pages, 2 figures, 1 table. Final version of manuscript accepted for 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). Implementation available at https://github.com/f90/AdversarialAudioSeparatio

Design techniques for high-performance current-steering digital-to-analog converters

Digital-to-Analog Converter (DAC) is a crucial building block limiting the accuracy and speed of many signal processing and telecommunication systems. To achieve high speed and high resolution, the current-steering architecture is almost exclusively used. Three important issues for current-steering DAC design are addressed in this dissertation. In a current-steering DAC design, it is essential that a designer determine the minimum required current source accuracy to overcome random current mismatch and achieve high linearity with guaranteed yield. Simple formulas are derived that clearly exhibit the relationship between the standard deviation of unit current sources, the bits of resolution, the INL/DNL, and the soft yield of DAC arrays. It is shown that these formulas are very effective for optimizing the DAC segmentation so as to achieve high performance and high yield with minimal area and power consumption. To overcome random mismatch effects without any trimming, the current source array of a high-accuracy DAC is usually rather large, causing the gradient errors in these arrays to become significant. How gradient errors affect the DAC linearity and how to compensate for them through switching sequence optimization is analyzed in the second part of this dissertation. To overcome technology barriers, relax the requirements on layout and reduce the sensitivities of DACs to process, temperature and aging, calibration is emerging as an attractive solution for the next-generation high-performance DACs, especially as process feature size keeps shrinking and supply voltage is reduced correspondingly. A new foreground calibration technique suitable for low-voltage environment is presented in the third part of this dissertation. It can effectively compensate for current source mismatches, and achieve high linearity with small die size and low power consumption. The dynamic performance of the DAC is also improved due to the dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit prototype was designed and fabricated in a 0.13u digital CMOS process. It is the first 14-bit CMOS DAC ever reported that operates with a single 1.5V power supply, occupies an active area less than 0.1mm2, and requires only 16.7mW at 100MHz sampling rate, but still maintains state-of-art linearity and speed

Drag-free and attitude control for the GOCE satellite

The paper concerns Drag-Free and Attitude Control of the European satellite Gravity field and steady-state Ocean Circulation Explorer (GOCE) during the science phase. Design has followed Embedded Model Control, where a spacecraft/environment discrete-time model becomes the realtime control core and is interfaced to actuators and sensors via tuneable feedback laws. Drag-free control implies cancelling non-gravitational forces and all torques, leaving the satellite to free fall subject only to gravity. In addition, for reasons of science, the spacecraft must be carefully aligned to the local orbital frame, retrieved from range and rate of a Global Positioning System receiver. Accurate drag-free and attitude control requires proportional and low-noise thrusting, which in turn raises the problem of propellant saving. Six-axis drag-free control is driven by accurate acceleration measurements provided by the mission payload. Their angular components must be combined with the star-tracker attitude so as to compensate accelerometer drift. Simulated results are presented and discusse

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Measurements, Models, Systems and Design

531 s.