2 research outputs found

    A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC

    No full text

    8-bit 50ksps ULV SAR ADC

    Get PDF
    With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient peripherals are needed. This project presents an Analog to Digital converter using ultra low supply voltage on transistor level. With a charge recycling spilt capacitive DAC using set and down switching method. And a comparator with a dynamic amplifier, resulted in a very energy efficient SAR ADC. The ADC got a samplings rate of 50k Hz and an ENOB of 7.89 bits, while only draining 75nW power from a 0.5V supply. This results in a Walden FOM of 7.39fJ/conv.step
    corecore