A tool for the automatic analysis of single events effects on electronic circuits

Nowadays integrated circuit reliability is challenged by both variability and working conditions. Environmental radiation has become a major issue when ensuring the circuit correct behavior. The required radiation and later analysis performed to the circuit boards is both fund and time expensive. The lack of tools which support pre-manufacturing radiation hardness analysis hinders circuit designers tasks. This paper describes an extensively customizable simulation tool for the characterization of radiation effects on electronic systems. The proposed tool can produce an in depth analysis of a complete circuit in almost any kind of radiation environment in affordable computation times

A crossbar network for silicon quantum dot qubits

Copyright © 2018 The Authors. The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. To increase the number of qubits to the thousands or millions of qubits needed for practical quantum information, we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for nonplanar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates enable qubit addressability and readout. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning-noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future

Enhancement in Reliability for Multi-core system consisting of One Instruction Cores

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of transient faults and permanent faults. The mitigation of transient faults and permanent faults at the core level has become an important design parameter in a multi-core scenario. Core level techniques is a redundancy-based fault mitigation technique that improves the lifetime reliability of multi-core systems. In an asymmetric multi-core system, the smaller cores provide fault tolerance to larger cores is a core level fault mitigation technique that has gained momentum and focus from many researchers. The paper presents an economical, asymmetric multi-core system with one instruction cores (MCSOIC). The term Hardware Cost Estimation signifies power and area estimation for MCS-OIC. In MCSOIC, OIC is a warm standby redundant core. OICs provide functional support to conventional cores for shorter periods of time. To evaluate the idea, different configurations of MCSOIC is synthesized using FPGA and ASIC. The maximum power overhead and maximum area overhead are 0.46% and 11.4% respectively. The behavior of OICs in MCS-OIC is modelled using a One-Shot System (OSS) model for reliability analysis. The model parameters namely, readiness, wakeup probability and start-up-strategy for OSS are mapped to the multi-core systems with OICs. Expressions for system reliability is derived. System reliability is estimated for special cases.Comment: 46 page

Runtime Verification of Analog and Mixed Signal Designs

Analog and mixed signal (AMS) circuits play an important role in system on chip designs. They pose, however, many challenges in the verification of the overall system due to their complex behaviors and expensive consumption of simulation resources. Besides functionality, AMS systems also suffer from stochastic processes such as random noise which exhibits statistical properties. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this thesis, we propose a methodology for the verification of AMS designs using functional and statistical runtime verification. Functional runtime verification is used to check the functional behavior of the AMS design. A system of recurrence equation (SRE) is used to model the AMS design and construct a functional property monitor. This functional runtime verification is carried out in an online fashion. Statistical runtime verification is used to verify the statistical properties of the AMS design. Hypothesis test, which is a method to make statistical decisions about rejecting or accepting some statement about the information of a sample, is used to verify the statistical properties. We use Monte Carlo simulation for the hypothesis test and for evaluating its performance. The proposed methodology is applied to a phase lock loop based frequency synthesizer where several functional properties and stochastic noise properties are verified