4 research outputs found

    Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

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    As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

    Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications

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    Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet of Things (IoT), cloud computing and etc. As the high-speed data symbol times shrink, this results in an increased amount of inter-symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity and consideration of advanced modulation schemes, such as four-level pulse amplitude modulation (PAM-4). Serial links which utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature (PVT) variations, benefits from improved area and power with CMOS technology scaling and offers easy design transfer between different technology nodes and thus improved time-to-market. However, ADC-based receivers generally consume higher power relative to their mixed-signal counterparts because of the significant power consumed by conventional multi-GS/s ADC implementations. This motivates exploration of energy-efficient ADC designs with moderate resolution and very high sampling rates to support data rates at or above 50Gb/s. This dissertation presents two power-efficient designs of ā‰„25GS/s time-interleaved ADCs for ADC-based wireline receivers. The first prototype includes the implementation of a 6b 25GS/s time-interleaved multi-bit search ADC in 65nm CMOS with a soft-decision selection algorithm that provides redundancy for relaxed track-and-hold (T/H) settling and improved metastability tolerance, achieving a figure-of-merit (FoM) of 143fJ/conversion step and 1.76pJ/bit for a PAM-4 receiver design. The second prototype features the design of a 52Gb/s PAM-4 ADC-based receiver in 65nm CMOS, where the front-end consists of a 4-stage continuous-time linear equalizer (CTLE)/variable gain amplifier (VGA) and a 6b 26GS/s time-interleaved SAR ADC with a comparator-assisted 2b/stage structure for reduced digital-to-analog converter (DAC) complexity and a 3-tap embedded feed-forward equalizer (FFE) for relaxed ADC resolution requirement. The receiver front-end achieves an efficiency of 4.53bJ/bit, while compensating for up to 31dB loss with DSP and no transmitter (TX) equalization

    A Capacitor-Less Wide-Band Power Supply Rejection Low Drop-Out Voltage Regulator with Capacitance Multiplier

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    A Low Drop-Out (LDO) voltage regulator with both capacitor-less and high power supply rejection (PSR) bandwidth attributes is highly admired for an integrated power management system of mobile electronics. The capacitor-less feature is demanded for realizing more compact device. The high PSR bandwidth is essential for being used with high frequency switching regulators. These two attributes are of strong trade-off because usually a capacitor-less LDO requires Miller Compensation which greatly limits the PSR bandwidth. This thesis presents a LDO design with both capacitor-less and high PSR bandwidth attributes. The proposed LDO structure incorporates external compensation which is gifted for extended PSR bandwidth. A capacitance multiplier (CM) of high multiplication factor (ā‰ˆ 100) is designed to externally compensate the LDO without an external off-chip capacitor. In the proposed LDO circuit, NMOS is used as the pass transistor for system stabilization. Triple-well NMOS and Zero-Vt NMOS are used as pass transistors in the two main LDO designs. The design with the triple-well NMOS pass transistor aims at higher PSR bandwidth with lower power consumption. The design with Zero-Vt NMOS pass transistor eliminates the necessity of a charge pump for driving the gate of a NMOS pass transistor. Implemented in IBM 0.18Ī¼m technology, the LDO with triple-well NMOS achieves -40dB PSR to 19MHz with 265Ī¼A current consumption. The LDO with Zero-Vt NMOS achieves -40dB PSR to 10MHz with 350Ī¼A current consumption. In thisdesign, the feasibility of using Zero-Vt NMOS as a LDO pass transistor is proved. Moreover, compared to traditional capacitor-less LDOs with PSR bandwidth around 10kHz and above 0dB PSR beyond 10MHz, the PSR bandwidth of the proposed LDO structure is greatly extended with significant PSR over 10MHz. This also proves the feasibility of applying external compensation strategy to a capacitor-less LDO and its great beneficial effect on the PSR of the LDO

    Equalization Architectures for High Speed ADC-Based Serial I/O Receivers

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    The growth in worldwide network traļ¬ƒc due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased serial I/O data rates over legacy channels with signiļ¬cant frequency-dependent attenuation. For these high-loss channel applications, ADC-based high-speed links are being considered due to their ability to enable powerful digital signal processing (DSP) algorithms for equalization and symbol detection. Relative to mixed-signal equalizers, digital implementations oļ¬€er robustness to process, voltage and temperature (PVT) variations, are easier to reconļ¬gure, and can leverage CMOS technology scaling in a straight-forward manner. Despite these advantages, ADC-based receivers are generally more complex and have higher power consumption relative to mixed-signal receivers. The ensuing digital equalization can also consume a signiļ¬cant amount of power which is comparable to the ADC contribution. Novel techniques to reduce complexity and improve power eļ¬ƒciency, both for the ADC and the subsequent digital equalization, are necessary. This dissertation presents eļ¬ƒcient modeling and implementation approaches for ADC-based serial I/O receivers. A statistical modeling framework is developed, which is able to capture ADC related errors, including quantization noise, INL/DNL errors and time interleaving mismatch errors. A novel 10GS/s hybrid ADC-based receiver, which combines both embedded and digital equalization, is then presented. Leveraging a time-interleaved asynchronous successive approximation ADC architecture, a new structure for 3-tap embedded FFE inside the ADC with low power/area overhead is used. In addition, a dynamically-enabled digital 4-tap FFE + 3-tap DFE equalizer architecture is introduced, which uses reliable symbol detection to achieve remarkable savings in the digital equalization power. Measurement results over several FR4 channels verify the accuracy of the modeling approach and the eļ¬€ectiveness of the proposed receiver. The comparison of the fabricated prototype against state-of-the-art ADC-based receivers shows the ability of the proposed archi-tecture to compensate for the highest loss channel, while achieving the best power eļ¬ƒciency among other works
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