Design of High-Speed Power-Efficient Transmitter with Time-Based Equalization

본 논문은 고속, 저전력으로 동작하는 유선 송신기의 설계에 대해 설명하고 있다. 분리되지 않은 출력 드라이버가 있는 에너지 효율적인 전압 모드 송신기는 위상 지연 분석을 기반으로 시간 영역에서 채널 손실을 보상한다. 직렬화된 데이터 스트림이 아닌 송신 클럭의 위상을 변조함으로써 제안된 송신기는 데이터 의존적 지터를 크게 줄인다. 수평 아이 오프닝은 전송된 데이터의 실행 길이에 따라 제로 크로싱 시간 변동을 보상함으로써 개선된다. 제안된 방식은 큰 신호 및 스위칭 전력을 소비하는 많은 드라이버 슬라이스를 제거함으로써 드라이버 복잡성을 크게 줄인다. 프로토타입 칩은 28 nm CMOS 공정으로 제작되었으며 0.045 mm2 의 실제 면적을 차지한다. 측정된 결과는 제안된 송신기가 1.0 V 공급에서 440 mVppd의 출력 스윙으로 22 Gb/s의 속도에서 0.95 pJ/b의 에너지 효율을 달성함을 보여준다. 또한 피크 대 피크 지터는 15.0 dB 손실의 채널에 대해 제안된 위상 지연 보상을 통해 22 Gb/s의 속도에서 34 ps에서 20 ps로 감소된다.In this thesis, a design of high-speed, power-efficient wireline transmitter is reported. An energy-efficient voltage-mode transmitter with an un-segmented output driver equalizes channel loss in the time-domain based on the phase de-lay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces the data-dependent jitter. The horizontal eye-opening is improved by compensating for the zero-crossing time variation dependent on the run-length of the transmitted data. The proposed scheme significantly reduces the driver complexity by elim-inating many driver slices that consume significant signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm2. The measured results show that the pro-posed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mVppd at 1.0 V supply. In addition, peak-to-peak jitter is reduced from 34 ps to 20 ps at 22 Gb/s with the proposed phase delay compen-sation over the channel with a 15.0 dB loss.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 FEED-FORWARD EQUALIZATION 7 2.2.1 AMPLITUDE-DOMAIN EQUALIZATION 7 2.2.2 PHASE-DOMAIN EQUALIZATION 12 2.2.3 PULSE-WIDTH MODULATION 18 2.3 ADAPTIVE FEED-FORWARD EQUALIZATION 21 2.3.1 AMPLITUDE-DOMAIN EQUALIZATION 21 2.3.2 PULSE-WIDTH MODULATION 24 CHAPTER 3 DESIGN OF THE TIME-BASED FEED-FORWARD EQUALIZATION OF THE TRANSMITTER 26 3.1 OVERVIEW 26 3.2 BASIC CONCEPT OF TIME-BASED FFE 28 3.2.1 ZERO-CROSSING TIME 28 3.2.2 PHASE DELAY 32 3.2.3 FINDING THE OPTIMUM COEFFICIENT 39 3.2.4 COMPARISON WITH CONVENTIONAL FFE 43 3.3 ADAPTIVE TIME-BASED FFE 50 3.3.1 OVERVIEW 50 3.3.2 BEHAVIORAL MODELING 51 3.3.3 SIMULATION RESULTS 53 3.4 TRANSMITTER IMPLEMENTATION 60 3.4.1 OVERVIEW 60 3.4.2 PHASE MODULATION 62 3.4.3 SERIALIZER AND CLOCK PATH 67 CHAPTER 4 MEASUREMENT 71 4.1 OVERVIEW 71 4.2 EYE DIAGRAM 76 4.3 POWER CONSUMPTION 81 CHAPTER 5 CONCLUSION 84 BIBLIOGRAPHY 86 초 록 92박

A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis

隨著CMOS製程持續進步，資料傳輸的速度也跟著快速成長。但隨著傳輸速度的提升，許多問題也開始出現，相對於傳輸資料的速度，傳輸通道的有限頻寬就是其中的一個問題，這問題會造成訊號失真與嚴重的符際干擾，在通訊系統中，會將等化器放置於傳送器或是放置於接收器以解決符際干擾問題。因為傳輸通道的材質和長度會隨著應用而有所不同，因此等化器會搭配一個可適性的演算法，使電路可工作在不同的通道。 本論文提出一個使用時間模式去加強法的可適性電壓模式傳送器。此時間模式去加強法是使用功率平衡法來決定責任週期，並利用脈波寬度調變來控制所需的補償增益。我們提出的可適性演算法不需要額外的輔助傳輸線，並且可以忍受製程變異。此電路實現於40奈米製程，其傳送器和接收器的面積各為0.075mm2和0.105mm2。在每秒50億位元的傳輸速率下，此傳送器能操作在通道損耗為15 dB的環境，且量測到的方均根抖動為12.25 ps，其位元錯誤率小於10-12。此電路的校正時間為2.048 us。在1.1伏特電壓操作下，此傳送器功率消耗9.3mW，而接收發器整體的功率消耗為17.5mW。With the CMOS technology continues to progress, the data rate is also fast growing in different applications. As data rate keeps rising, many significant problems appear. One of the problem is that the channel bandwidth limits compared with the data rate. It will result in a significant inter symbol interference (ISI) and cause signal distortion. In communication systems, equalizers are widely adopted in transmitter side or receiver side to deal with ISI. The length or the material of the transmission channel may be different for various applications. Therefore, an equalizer with the adaptive algorithm is widely adopted in communication systems. A 5-Gb/s adaptive voltage-mode (VM) transmitter using time-based de-emphasis is presented. The duty cycle of the pulse width modulation is adjusted by the spectrum-balancing technique. For different cable lengths, the duty cycle of the PWM data is adaptively adjusted. The proposed adaptive VM transmitter does not require any auxiliary channels. The proposed adaptive VM transmitter can tolerate the process variations. This adaptive transmitter is fabricated in a 40-nm CMOS process. The active areas of the transmitter and the receiver are 0.075mm2 and 0.105mm2, respectively. For a 5-Gb/s PRBS of 27-1 passing through a 9-m coaxial cable with a 15.35-dB loss, the measured root-mean-square jitters of the recovered data is 12.25 ps. The measured bit error rate is less than 10-12. The settling time for adaptive time-based de-emphasis is 2.048us. For a 1.1V supply voltage, the power of the transmitter is 9.3mW and the total power of the transceiver is 17.5mW