Screen printable flexible BiTe-SbTe based composite thermoelectric materials on textiles for wearable applications

This paper presents the optimization of a bismuth tellurium (Bi1.8Te3.2)-antimony tellurium (Sb2Te3)-based thermoelectric generator (TEG) fabricated by screen-printing technology on flexible polyimide (Kapton) and textile substrates. New formulations of screen printable thermoelectric pastes are presented with optimized composition, curing conditions, and printing parameters. The modifications of the thermoelectric materials enable them to be successfully deposited on flexible textile substrates. The optimized values of resistivity of the BiTe and SbTe thick films on Kapton were 9.97 × 10-3 and 3.57 × 10-3 ? · cm, respectively. The measured figure of merit at room temperature was 0.135 and 0.095 for BiTe and SbTe thick films on Kapton, respectively. The dimension of each printed thermoleg was 20 mm×2 mm×70.5 ?m. For the TEG on Kapton, the printed assembly comprising eight thermocouples was coiled up and generated a voltage of 26.6 mV and a maximum power output of 455.4 nW at a temperature difference of 20 °C. For a printed TEG on textile, the maximum power output reached 2 ?W from the same temperature difference

A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 μm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis.ASTAR (Agency for Sci., Tech. and Research, S’pore)Accepted versio

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W