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    SRAM PUF์˜ ์‹ ๋ขฐ์„ฑ ๊ฐœ์„ ์„ ์œ„ํ•œ ์ „์› ๊ณต๊ธ‰ ๊ธฐ๋ฒ•

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    ํ•™์œ„๋…ผ๋ฌธ (์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ์œตํ•ฉ๊ณผํ•™๊ธฐ์ˆ ๋Œ€ํ•™์› ์œตํ•ฉ๊ณผํ•™๋ถ€(์ง€๋Šฅํ˜•์œตํ•ฉ์‹œ์Šคํ…œ์ „๊ณต), 2021. 2. ์ „๋™์„.PUF (Physically Unclonable Function)์€ ํ•˜๋“œ์›จ์–ด ๋ ˆ๋ฒจ์˜ ์ธ์ฆ ๊ณผ ์ •์—์„œ ๋„๋ฆฌ ์ด์šฉ๋˜๋Š” ๋ฐฉ๋ฒ•์ด๋‹ค. ๊ทธ ์ค‘์—์„œ๋„ SRAM PUF๋Š” ๊ฐ€์žฅ ์ž˜ ์•Œ ๋ ค์ง„ PUF์˜ ๋ฐฉ๋ฒ•๋ก ์ด๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ์˜ˆ์ธก ๋ถˆ๊ฐ€๋Šฅํ•œ ๋™์ž‘์œผ๋กœ ์ธํ•ด ๋ฐœ์ƒ๋˜๋Š” ๋‚ฎ์€ ์žฌ์ƒ์‚ฐ์„ฑ๊ณผ ์ „์› ๊ณต๊ธ‰ ๊ณผ์ •์—์„œ ๋ฐœ์ƒํ•˜๋Š” ๋…ธ์ด์ฆˆ์˜ ๋ฌธ์ œ๋ฅผ ๊ฐ€์ง€๊ณ  ์žˆ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ํšจ๊ณผ์ ์œผ๋กœ SRAM PUF์˜ ์žฌ์ƒ์‚ฐ์„ฑ์„ ํ–ฅ์ƒ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋Š” ๋‘ ๊ฐ€์ง€ ์ „์› ๊ณต๊ธ‰ ๊ธฐ๋ฒ•์„ ์ œ์•ˆํ•œ๋‹ค. ์ œ์‹œํ•œ ๊ธฐ๋ฒ•๋“ค์€ ๊ฐ’์ด ์‚ฐ์ถœ๋˜ ๋Š” ์˜์—ญ ํ˜น์€ ์ „์› ๊ณต๊ธ‰์›์˜ ๊ธฐ์šธ๊ธฐ(ramp-up ์‹œ๊ฐ„)๋ฅผ ์กฐ์ ˆํ•จ์œผ๋กœ์จ ์› ํ•˜์ง€ ์•Š๋Š” ๋น„ํŠธ์˜ ๋’ค์ง‘ํž˜(flipping) ํ˜„์ƒ์„ ์ค„์ธ๋‹ค. 180nm ๊ณต์ •์œผ๋กœ ์ œ ์ž‘๋œ ํ…Œ์ŠคํŠธ ์นฉ์„ ์ด์šฉํ•œ ์ธก์ • ๊ฒฐ๊ณผ ์žฌ์ƒ์‚ฐ์„ฑ์ด 2.2๋ฐฐ ํ–ฅ์ƒ๋˜์—ˆ์„ ๋ฟ๋งŒ ์•„๋‹ˆ๋ผ NUBs(Native Unstable Bits)๋Š” 54.87% ๊ทธ๋ฆฌ๊ณ  BER (Bit Error Rate)๋Š” 55.05% ๊ฐ์†Œํ•œ ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค.Physically unclonable function (PUF) is a widely used hardware-level identification method. SRAM-based PUFs are the most well-known PUF topology, but they typically suffer from low reproducibility due to non-deterministic behaviors and noise during power-up process. In this work, we propose two power-up control techniques that effectively improve reproducibility of the SRAM PUFs. The techniques reduce undesirable bit flipping during evaluation by controlling either evaluation region or power supply ramp-up speed. Measurement results from the 180 nm test chip confirm that native unstable bits (NUBs) are reduced by 54.87% and bit error rate (BER) decreases by 55.05% while reproducibility increases by 2.2ร—.Chapter 1 Introduction 1 1.1 PUF in Hardware Securit 1 1.2 Prior Works and Motivation 2 Chapter 2 Related works and Motivation 5 2.1 Uniqueness 7 2.2 Reproducibility 7 2.3 Hold Static Noise Margin (SNM) 8 2.4 Bit Error Rate (BER) 9 2.5 PUF Static Noise Margin Ratio (PSNMratio) 9 Chapter 3 Microarchitecture-Aware Code Generation 11 3.1 Scheme 1: Developing Fingerprint in Sub-Threshold Region 13 3.2 Scheme 2: Controlling Voltage Ramp-up Speed 17 Chapter 4 Experimental Evaluation 19 4.1 Experimental Setup 19 4.2 Evaluation Results 21 Chapter 5 Conclusion 28 Bibliography 29 Abstract in Korean 33Maste
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