A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

A differential transceiver achieves a 40 mVppd channel signal-swing, a 9 mVppd receiver (RX) input sensitivity, and a 0.59 pJ/b energy efficiency at 9 Gb/s with a 12" FR-4 channel. A current-integrating TIA (CI-TIA) is proposed as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9 Gb/s. The RX circuit alone works up to 11 Gb/s with a 1" FR-4 channel. A voltage-mode pre-emphasis equalizer is combined with a current-mode logic (CML) driver at transmitter (TX) to save the low-frequency de-emphasis current of the conventional current-mode equalizer combined with a CML driver. The voltage-mode equalizer consists of a series connection of an inverter and a capacitor; the equalization coefficient is proportional to the supply voltage of the inverter. The transceiver chip in a 65 nm CMOS process consumes 2.8 mW at TX and 2.5 mW at RX with a 1 V supply and a 12" FR-4 channel at 9 Gb/s.1154sciescopu

A High-speed and Low Power Electrical Link Transceiver

On-chip wires will present increasing latency and energy problems as VLSI technologies continue to scale. Interconnects have an RC-limited bandwidth approximately proportional to the area of the metal cross section and inversely proportional to the squared length. To overcome RC-limited channels, an energy-efficient on-chip transceiver is presented that contains a hybrid transmitter, a current-sense receiver, and self-testing blocks. The main goal of this research is having a relatively low-power transceiver, which can be used as an on-chip communication system. By adding a pre-emphasis circuit in the transmitter, pre-cursor inter-symbol interference can be canceled. A hybrid transmitter which combines voltage-mode pre-emphasis with a current-mode main driver is used. This structure can save pre-emphasis current, and leads to reduced power dissipation especially in the static situation. A current-sense amplifier is implemented with a cross-coupled stage and an active inductor equalizer at the receiver, in order to boost the data rate while maintaining good energy efficiency. An offset cancelation circuit is incorporated to make a robust comparator for the receiver. According to simulation results, the transceiver has low power consumption with 1.2 V, 130 nm CMOS technology. The performance shows that it operates at 8 Gb/s over a 5 mm and 19 dB loss differential channel. The overall dynamic power consumption is 2.05 mW, without the PRBS generator/checker. Therefore, this transceiver has high data rate and low power consumption