A 3.5 Gsymbol/lane Receiver Design for MIPI C-PHY Layer v2.0

Department of Electrical EngineeringSemiconductor process technologies are the backbone of information driven era, where one can have an access to immense amount of data on a daily basis. As an amount of information continually increases, demand for advanced technology nodes follows the similar trend by evolving down to 3 nm process in 2022. Need for more information directly correlates with a need for higher speed of communication between data canters and clients. Higher operating speed brings up requirement for high power and surgical precision into a play. This power and speed trade-off can be the limiting factor in many systems, and designing high speed system while maintaining low or moderate power consumption requires engineers to invent more elaborate schemes that employ the above trade-off in the most efficient way. Other crucial aspects such as noise, communication efficiency, budget and area are also parameters in power and speed trade-off function that should be taken into careful consideration. Therefore, bridge systems are being developed in an effort to deliver vast of amount information between two or more communicating system, meanwhile aiming to optimize the aforementioned parameters._x000D_ Recently, a great deal of researches has been conducted to implement interfaces that provides high throughput and performance over bandlimited communication mediums. Due to manufacturing cost, designed systems architecture should be standardized to allow cross-compatibility over various devices. One of the such industry standard interface systems that found use in smartphones, smart watches, smart meters, video game devices, etc., is Mobile Industry Processor Interface Display/Camera Serial Interface (MIPI DSI/CSI). MIPI DSI/CSI enables high performance, low power solution while ensuring interoperability across different vendors. _x000D_ This thesis presents design of front end at 7.98 Gb/s for C-PHY (MIPI DSI/CSI physical layer) serial interface in TSMC-28 nm HPC CMOS technology. High-speed front end consists of termination resistor (RT), continuous time linear equalizer (CTLE), high-speed receiver (HSRX), clock and data recovery (CDR) circuit, decoder (DEC) and 7x21 de-serializer (DESER). RT block employs parallel trimming technique to ensure operation across PVT corners. Active CTLE improves signal integrity and accommodates trimming option to allow operation with different channel lengths. In order to recover the clock embedded into signal according to the C-PHY specification, CDR block is designed. DEC decodes output signals from HSRX in a fashion consistent with C-PHY specifications. As a result, analog frond end achieves less than 0.2 pJ/but efficiency with 0.9 V supply voltage._x000D_ope