A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator

\u3cp\u3eThis paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a g\u3csub\u3em\u3c/sub\u3e-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.\u3c/p\u3