3 research outputs found
Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems
With the increasing digital services demand, performance and power-efficiency
become vital requirements for digital circuits and systems. However, the
enabling CMOS technology scaling has been facing significant challenges of
device uncertainties, such as process, voltage, and temperature variations. To
ensure system reliability, worst-case corner assumptions are usually made in
each design level. However, the over-pessimistic worst-case margin leads to
unnecessary power waste and performance loss as high as 2.2x. Since
optimizations are traditionally confined to each specific level, those safe
margins can hardly be properly exploited.
To tackle the challenge, it is therefore advised in this Ph.D. thesis to
perform a cross-layer optimization for digital signal processing circuits and
systems, to achieve a global balance of power consumption and output quality.
To conclude, the traditional over-pessimistic worst-case approach leads to
huge power waste. In contrast, the adaptive voltage scaling approach saves
power (25% for the CORDIC application) by providing a just-needed supply
voltage. The power saving is maximized (46% for CORDIC) when a more aggressive
voltage over-scaling scheme is applied. These sparsely occurred circuit errors
produced by aggressive voltage over-scaling are mitigated by higher level error
resilient designs. For functions like FFT and CORDIC, smart error mitigation
schemes were proposed to enhance reliability (soft-errors and timing-errors,
respectively). Applications like Massive MIMO systems are robust against lower
level errors, thanks to the intrinsically redundant antennas. This property
makes it applicable to embrace digital hardware that trades quality for power
savings.Comment: 190 page
A 13 bits 4.096 GHz 45 nm CMOS Digital Decimation Filter Chain Using Carry-Save Format Numbers
status: publishe
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers
In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area