A Fully integrated D-band Direct-Conversion I/Q Transmitter and Receiver Chipset in SiGe BiCMOS Technology

This paper presents design and characterization of single-chip 110-170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and x6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3 dB RF bandwidth of 28 GHz from 112-140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm x 1.1 mm

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology