Estudo de um SAR ADC com DAC C-2C

O ADC de Registo de Aproximações Sucessivas (SAR) apresenta diversas vantagens face a outros conversores, nomeadamente, uma área reduzida, um baixo consumo de energia e pode ser utilizado para resoluções mais altas com uma velocidade de conversão moderada, pelo que é diversas vezes utilizado para redes de sensores sem fios e produtos biomédicos. Este tipo de Conversor Analógico-Digital beneficia, assim,do avanço tecnológico.O principal objetivo desta dissertação é o estudo de um SAR ADC com Conversor Digital-Analógico C-2C. Este tipo de arquitetura é pouco utilizada para conversores do tipo SAR daí que o DAC usualmente utilizado entre os autores é o DAC Pesado Binariamente. Contudo,o DAC C-2C apesar de ser pouco conhecido e utilizado apresenta as suas vantagens em relação ao DAC Pesado Binariamente.Inicialmente, o DAC C-2C é alvo de um estudo teórico no domínio da tensão, tendo como finalidade o desenvolvimento de um modelo de alto nível a partir do simulador MATLAB, o que permitiu resultados ao nível do processo de conversão do ADC para diferentes cenários e o estudo do ponto de vista da linearidade e de eficiência energética.Por fim,e perante diferentes tópicos de estudo é elaborada uma análise comparativa entre os dois DACs mencionados anteriormente. Este estudo permitiu verificar que o DAC C-2C apresenta vantagens em relação ao DAC Pesado Binariamente, nomeadamente ao nível da área e eficiência energética.The ADC of Successive Approximation Register (SAR) has several advantages over other converters namely, a reduced area, a low power consumption, and can be used for higher resolutions with a moderate conversion speed so it is often used for wireless sensor networks and biomedical products. This type of Analog-to-Digital Converter thus benefits from technological advancement.The main objective of this dissertation is the study of a SAR ADC with C-2C Digital -to -Analog Converter. This type of architecture is seldom used for converters of the SAR type, hence the DAC usually used among authors is the Binary Weighted DAC. However, C-2C DAC despite being little known and used has its advantages over Binary Weighted DAC.Initially, the DAC C-2C is the target of a theoretical study in the voltage domain, with the purpose of developing a high level model from the MATLAB simulator, which allowed results at the level of the ADC conversion process for different sce-narios and the study from the point of view of linearity and energy efficiency.Finally, and in view of different study topics, a comparative analysis is made between the two DAGs mentioned above. This study allowed us to verify that the DAC C-2C has advantages over the Binary Weighted DAC, namely in terms of area and energy efficiency

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd