A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe

Design of hybrid continuous-time discrete-time delta-sigma modulators

Recent attention has been drawn to the hybrid Delta-Sigma (ΔΣ) structure featuring the integration of continuous-time (CT) and discrete-time (DT) structures in the loop filter. It combines the accurate loop filter characteristic of a DT ΔΣ modulator and the inherent anti-aliasing of a CT ΔΣ modulator. We present a design methodology for building a CT-DT ΔΣ modulator via the transformation from a DT ΔΣ modulator prototype. We also demonstrate the tradeoff of applying this structure to cascaded Delta-Sigma modulators compared to pure CT or DT implementations. ©2008 IEEE.published_or_final_versio

A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe