4 research outputs found
๋ฉ๋ชจ๋ฆฌ ์ธํฐํ์ด์ค๋ฅผ ์ํ ๋ฉํฐ ๋ ๋ฒจ ๋จ์ผ ์ข ๋จ ์ก์ ๊ธฐ ์ค๊ณ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2020. 8. ๊น์ํ.๋ณธ ์ฐ๊ตฌ์์ ๋ฉ๋ชจ๋ฆฌ ์ธํฐํ์ด์ค๋ฅผ ์ํ ๋ฉํฐ ๋ ๋ฒจ ์ก์ ๊ธฐ๊ฐ ์ ์๋์๋ค. ํ๋ก์ธ์์ ๋ฉ๋ชจ๋ฆฌ ๊ฐ์ ์ฑ๋ฅ ์ฐจ์ด๊ฐ ๋งค๋
๊ณ์ ์ฆ๊ฐํจ์ ๋ฐ๋ผ, ๋ฉ๋ชจ๋ฆฌ๋ ์ ์ฒด ์์คํ
์ ๋ณ๋ชฉ์ ์ด ๋๊ณ ์๋ค. ์ฐ๋ฆฌ๋ ๋ฉ๋ชจ๋ฆฌ ๋์ญํญ์ ๋๋ฆฌ๊ธฐ ์ํด PAM-4 ๋จ์ผ ์ข
๋จ ์ก์ ๊ธฐ๋ฅผ ์ ์ํ์๊ณ , ๋ฉํฐ ๋ญํฌ ๋ฉ๋ชจ๋ฆฌ๋ฅผ ์ํ duobinary ๋จ์ผ ์ข
๋จ ์ก์ ๊ธฐ๋ฅผ ์ ์ํ์๋ค.
์ ์๋ PAM-4 ์ก์ ๊ธฐ์ ๋๋ผ์ด๋ฒ๋ ๋์ ์ ํ์ฑ๊ณผ ์ํผ๋์ค ์ ํฉ์ ๋์์ ๋ง์กฑํ๋ค. ๋ํ ์ ํญ์ด๋ ์ธ๋ํฐ๋ฅผ ์ฌ์ฉํ์ง ์์ ์์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์๋ ZQ ์บ๋ฆฌ๋ธ๋ ์ด์
์ ์ธ๊ฐ์ ๊ต์ ์ ์ ๊ฐ์ง๊ณ ์์ด ์ก์ ๊ธฐ๊ฐ ์ ํํ ์ํผ๋์ค์ ์ ํ์ ์ธ ์ถ๋ ฅ์ ๊ฐ๊ฒ ํ๋ค. ํ๋กํ ํ์
์ 65nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์๊ณ ์ก์ ๊ธฐ๋ 0.0333mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ธก์ ๋ 28Gb/s์์์ eye๋ 18.3ps์ ๊ธธ์ด์ 42.4mV์ ๋์ด๋ฅผ ๊ฐ๊ณ , ์๋์ง ํจ์จ์ 0.64pJ/bit์ด๋ค. ZQ ์บ๋ฆฌ๋ธ๋ ์ด์
๊ณผ ํจ๊ป ์ธก์ ๋ RLM์ 0.993์ด๋ค.
๋ฉ๋ชจ๋ฆฌ์ ์ฉ๋์ ๋๋ฆฌ๊ธฐ ์ํด ํ๋์ ํจํค์ง์ ์ฌ๋ฌ ๊ฐ์ DRAM ๋ค์ด๋ฅผ ์์ง์ผ๋ก ์๋ ํจํค์ง์ ๋ฉ๋ชจ๋ฆฌ์ ์ค์ ํจ๋ ๊ตฌ์กฐ์ ๊ฒฐํฉ๋์ด ์งง์ ๋ฐ์ฌ๋ฅผ ์ผ๊ธฐํ๋ ์คํ
์ ๋ง๋ ๋ค. ์ฐ๋ฆฌ๋ ์ด ๋ฌธ์ ๋ฅผ ์ํํ๊ธฐ์ํด ๋ฐ์ฌ ๊ธฐ๋ฐ duobinary ์ก์ ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ด ์ก์ ๊ธฐ๋ ๋ฐ์ฌ๋ฅผ ์ด์ฉํ์ฌ duobinary signaling์ ํ๋ค. 2ํญ ๋ฐ๋ ๊ฐ์กฐ ๊ธฐ์ ๊ณผ ์ฌ๋ฃจ ๋ ์ดํธ ์กฐ์ ๊ธฐ์ ์ด ์ ํธ ์๊ฒฐ์ฑ์ ๋์ด๊ธฐ ์ํด ์ฌ์ฉ๋์๋ค. NRZ eye๊ฐ ์๋ 10Gb/s์์ ์ธก์ ๋ duobinary eye๋ 63.6ps ๊ธธ์ด์ 70.8mV์ ๋์ด๋ฅผ ๊ฐ๋๋ค. ์ธก์ ๋ ์๋์ง ํจ์จ์ 1.38pJ/bit์ด๋ค.Multi-level transmitters for memory interfaces have been presented. The performance gap between processor and memory has been increased by 50% every year, making memory to be a bottle neck of the overall system. To increase memory bandwidth, we have proposed a PAM-4 single-ended transmitter. To compensate for the side effect of the multi-rank memory, we have proposed a reflection-based duobinary transmitter.
The proposed PAM-4 transmitter has the driver, which simultaneously satisfies impedance matching and high linearity. The driver occupies a small area due to a resistorless and inductorless structure. The proposed ZQ calibration for PAM-4 has three calibration points, which allow the transmitter to have accurate impedance and linear output. The ZQ calibration considers impedance variation of both the driver and the receiver. A prototype has been fabricated in 65nm CMOS process, and the transmitter occupies 0.0333mm2. The measured eye has a width of 18.3ps and a height of 42.4mV at 28Gb/s, and the measured energy efficiency is 0.64pJ/b. The measured RLM with the 3-point ZQ calibration is 0.993.
To increase memory density, the stacked die packaging with multiple DRAM die stacked vertically in one package is widely used. However, combined with the center-pad structure, the structure creates stubs that cause short reflections. We have proposed the reflection-based duobinary transmitter to mitigate this problem. The proposed transmitter uses reflection for duobinary signaling. The 2-tap opposite FFE and the slew-rate control are used to increase signal integrity. The measured duobinary eye at 10Gb/s has a width of 63.6ps and a height of 70.8mV while there is no NRZ eye opening. The measured energy efficiency is 1.38pJ/bit.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 8
CHAPTER 2 MUTI-LEVEL SIGNALING 9
2.1 PAM-4 SIGNALING 9
2.2 DESIGN CONSIDERATIONS FOR PAM-4 TRANSMITTER 16
2.2.1 LEVEL SEPARATION MISMATCH RATIO (RLM) 17
2.2.2 IMPEDANCE MATCHING 19
2.2.3 PRIOR ARTS 21
2.3 DUOBINARY SIGNALING 24
CHAPTER 3 HIGH-LINEARITY AND IMPEDANCE-MATCHED PAM-4 TRANSMITTER 30
3.1 OVERALL ARCHITECTURE 31
3.2 SINGLE-ENDED IMPEDANCE-MATCHED PAM-4 DRIVER 33
3.3 3-POINT ZQ CALIBRATION FOR PAM-4 47
CHAPTER 4 REFLECTION-BASED DUOBINARY TRANSMITTER 57
4.1 BIDIRECTIONAL DUAL-RANK MEMORY SYSTEM 58
4.2 CONCEPT OF REFLECTION-BASED DUOBINARY SIGNALING 66
4.3 REFLECTION-BASED DUOBINARY TRANSMITTER 70
4.3.1 OVERALL ARCHITECTURE 70
4.3.2 EQUALIZATION FOR REFLECTION-BASED DUOBINARY SIGNALING 72
4.3.3 2D BINARY-SEGMENTED DRIVER 75
CHAPTER 5 EXPERIMENTAL RESULTS 77
5.1 HIGH-LINEARITY AND IMPEDANCE-MATCHED PAM-4 TRANSMITTER 77
5.2 REFLECTION-BASED DUOBINARY TRANSMITTER 84
CHAPTER 6 92
CONCLUSION 92
BIBLIOGRAPHY 94Docto
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Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems
Ever increasing global internet data tra๏ฌc has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals su๏ฌering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization.
In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-e๏ฌcient way on bandwidth-limited wireline channels without using conventional equalizers or ๏ฌlters.
The ๏ฌrst topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an e๏ฌciency of 8.66 pJ/bit in 65 nm CMOS.
The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or ๏ฌlters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10โ12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit e๏ฌciency while operating at 13.6 Gb/s and 16 Gb/s, respectively
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