A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines

This paper presents a 107GHz LNA prototype using TSMC 65nm CMOS technology. It explores the limit of the CMOS technology by effectively optimizing the active and passive devices. An improvement of 1.6dB higher maximum stable/available gain (MSG/MAG) on the transistor is achieved around 110GHz by layout optimization and inductor neutralization technique. A high quality factor co-planar waveguide (CPW) transmission line is designed utilizing the slow-wave effect. A quality factor of 23.6 is demonstrated by EM-simulations while taken the consideration of satisfying the stringent layout design rules. Based on the optimization on the active and passive devices, a dual-stage LNA is designed, with a simulated power gain of 10.2dB and noise figure of 8dB at 107GHz, verified by chip-level EM-simulations. The power consumption is 28.2mW

A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines

This paper presents a 107GHz LNA prototype using TSMC 65nm CMOS technology. It explores the limit of the CMOS technology by effectively optimizing the active and passive devices. An improvement of 1.6dB higher maximum stable/available gain (MSG/MAG) on the transistor is achieved around 110GHz by layout optimization and inductor neutralization technique. A high quality factor co-planar waveguide (CPW) transmission line is designed utilizing the slow-wave effect. A quality factor of 23.6 is demonstrated by EM-simulations while taken the consideration of satisfying the stringent layout design rules. Based on the optimization on the active and passive devices, a dual-stage LNA is designed, with a simulated power gain of 10.2dB and noise figure of 8dB at 107GHz, verified by chip-level EM-simulations. The power consumption is 28.2mW