A 12-bit Successive Approximation Register Analog to Digital converter for Space Application in 22nm CMOS Technology

We propose a 12-bit successive approximation register (SAR)-analog to digital converter (ADC) in 22nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS Technology. The proposed ADC is implemented with radiation-hardened techniques to guarantee its operation in the space environment. Single-event transient (SET) which is one of critical radiation-strike effects suffers from non-linearity error or non-monotonic. The redundancy techniques are used for preventing failures of circuits caused by SET effects. The comparator uses Triple-Modular Redundancy (TMR) technique, and the serial switch scheme is applied for capacitive Digital-Analog Converter (CDAC) block. SETs are simulated on sub-blocks of the SAR-ADC to confirm the improvement against the degradation caused by the radiation effect

A 4-channel 12-bit high-voltage radiation-hardened digital-to-analog converter for low orbit satellite applications

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-μm Bi-CMOS technology to achieve the functionality across a wide-temperature range from -55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of -0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from -55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm x 7 mm in total including pads (core active area of 4 mm x 5 mm excluding pads) and consumes less than 525 mW, output voltage ranges from -10 to +10 V