SAW-Less Digitally-Assisted Receivers

Today’s wireless devices, like our smartphones, are able to handle multiple standards and bands for different applications, such as Bluetooth, Wi-Fi and data-voice communications. However, the cost of a modern transceiver is becoming mainly dominated by the large number of off-chip passive components, like Duplexers and SAW filters, needed to distinguish the desired signal among many interferences. Addressing the challenges that arise from the lack of RF filtering, a SAW-less architecture represents an interesting solution to reduce the platform complexity. This thesis proposes a feasible solution based on a SAW-less RF front-end able to meet the standard requirements and a digital system tailored to the RF path. The digital architecture, which represents the main topic of this thesis, is described in detail and experimentally tested to validate the proposed solutions

A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS

The first integrated duplexer compatible with a -15dBm RX blocker for up to 23dBm TX power is reported. A three winding transformer is driven at the primary by a single ended PA and drives a differential push-pull common-gate LNA. Only 45 dB isolation is required thanks to the 23 dBm RX IIP3 drastically simplifying hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA and base-band stays below 6.7dB and the TX insertion loss below 4 dB from 1.6 to 2.2 GHz. The chip is implemented in 28nm CMOS has an active area of 0.7mm2 and uses only 26mW