3 research outputs found
Design of High-Speed Power-Efficient Transmitter with Time-Based Equalization
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μΉ©μ 28 nm CMOS 곡μ μΌλ‘ μ μλμμΌλ©° 0.045 mm2 μ μ€μ λ©΄μ μ μ°¨μ§νλ€. μΈ‘μ λ κ²°κ³Όλ μ μλ μ‘μ κΈ°κ° 1.0 V 곡κΈμμ 440 mVppdμ μΆλ ₯ μ€μμΌλ‘ 22 Gb/sμ μλμμ 0.95 pJ/bμ μλμ§ ν¨μ¨μ λ¬μ±ν¨μ 보μ¬μ€λ€. λν νΌν¬ λ νΌν¬ μ§ν°λ 15.0 dB μμ€μ μ±λμ λν΄ μ μλ μμ μ§μ° 보μμ ν΅ν΄ 22 Gb/sμ μλμμ 34 psμμ 20 psλ‘ κ°μλλ€.In this thesis, a design of high-speed, power-efficient wireline transmitter is reported. An energy-efficient voltage-mode transmitter with an un-segmented output driver equalizes channel loss in the time-domain based on the phase de-lay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces the data-dependent jitter. The horizontal eye-opening is improved by compensating for the zero-crossing time variation dependent on the run-length of the transmitted data. The proposed scheme significantly reduces the driver complexity by elim-inating many driver slices that consume significant signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm2. The measured results show that the pro-posed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mVppd at 1.0 V supply. In addition, peak-to-peak jitter is reduced from 34 ps to 20 ps at 22 Gb/s with the proposed phase delay compen-sation over the channel with a 15.0 dB loss.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 4
CHAPTER 2 BACKGROUNDS 5
2.1 OVERVIEW 5
2.2 FEED-FORWARD EQUALIZATION 7
2.2.1 AMPLITUDE-DOMAIN EQUALIZATION 7
2.2.2 PHASE-DOMAIN EQUALIZATION 12
2.2.3 PULSE-WIDTH MODULATION 18
2.3 ADAPTIVE FEED-FORWARD EQUALIZATION 21
2.3.1 AMPLITUDE-DOMAIN EQUALIZATION 21
2.3.2 PULSE-WIDTH MODULATION 24
CHAPTER 3 DESIGN OF THE TIME-BASED FEED-FORWARD EQUALIZATION OF THE TRANSMITTER 26
3.1 OVERVIEW 26
3.2 BASIC CONCEPT OF TIME-BASED FFE 28
3.2.1 ZERO-CROSSING TIME 28
3.2.2 PHASE DELAY 32
3.2.3 FINDING THE OPTIMUM COEFFICIENT 39
3.2.4 COMPARISON WITH CONVENTIONAL FFE 43
3.3 ADAPTIVE TIME-BASED FFE 50
3.3.1 OVERVIEW 50
3.3.2 BEHAVIORAL MODELING 51
3.3.3 SIMULATION RESULTS 53
3.4 TRANSMITTER IMPLEMENTATION 60
3.4.1 OVERVIEW 60
3.4.2 PHASE MODULATION 62
3.4.3 SERIALIZER AND CLOCK PATH 67
CHAPTER 4 MEASUREMENT 71
4.1 OVERVIEW 71
4.2 EYE DIAGRAM 76
4.3 POWER CONSUMPTION 81
CHAPTER 5 CONCLUSION 84
BIBLIOGRAPHY 86
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Speech Recognition
Chapters in the first part of the book cover all the essential speech processing techniques for building robust, automatic speech recognition systems: the representation for speech signals and the methods for speech-features extraction, acoustic and language modeling, efficient algorithms for searching the hypothesis space, and multimodal approaches to speech recognition. The last part of the book is devoted to other speech processing applications that can use the information from automatic speech recognition for speaker identification and tracking, for prosody modeling in emotion-detection systems and in other speech processing applications that are able to operate in real-world environments, like mobile communication services and smart homes