A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance

Radio receivers should be robust to large out-of-band blockers with small degradation in their sensitivity. N-path mixers can be used as mixer-first receivers [1] with good linearity and RF filtering [2]. However, 1/f noise calls for large active device sizes for IF circuits and high power consumption. The 1/f noise issue can be relaxed by having RF gain. However, to avoid desensitization by large out-of-band blockers, a bandpass filter (BPF) with sharp cut-off frequency is required in front of the RF amplifiers. gm-C BPFs suffer from tight tradeoffs among DR, power consumption, Q and fc. Also, on-chip Q-enhanced LC BPFs [3] are not suitable due to low DR, large area and non-tunability. Therefore, bulky and non-tunable SAW filters are used. N-path BPFs offer high Q while their center frequency is tuned by the clock frequency [2]. Compared to gm-C filters, this technique decouples the required Q from the DR. The 4-path filter in [4] has only 2nd-order filtering and limited rejection. The order and rejection of N-path BPFs can be increased by cascading [5], but this renders a “round” passband shape. The 4th-order 4-path BPF in [6] has a “flat” passband shape and high rejection but a high NF. This work solves the noise issue of [6] while achieving the same out-of-band linearity and adding 25dB of voltage gain to relax the noise requirement of the subsequent stages

Design and Analysis of N-path Filter for Radio Frequencies

Due to the growth of wireless communication many communication frequencies have grown increasingly dense. This density requires higher Q-factor to receive only the signal of interest. With the rise of smaller integrated circuits previous solutions used for filtering have become viable again. This paper explores whether the N-path filter is viable in the modern day for radio frequency receiver purposes. A non-differential N-path filter was created by utilizing Cadence Virtuoso with a working center frequency range of 750MHz to 1GHz while using TSMC technology. The desired quality factor of over 1,000 was reached while maintaining a total area of 800 by 800 micrometers. Through the analysis of the N-path filter new techniques for mixed signal analysis were used for simulation. This included parametric analysis in Cadence ADE-L and additional analysis in MATLAB, and the addition of a bootstrapping circuit to decrease simulation time. Future applications regarding analyzing mixed signals could use these methods to provide frequency response data and automated processing

Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog) domain into utilizing charge or time as the variable that can be processed by mostly digital/passive circuits. In this thesis, both circuit-level techniques and architectures are proposed that are inherently compatible with transistor scaling in submicron CMOS, meanwhile achieving state-of-the-art performance and optimizing power efficiency. The first part focuses on a highly reconfigurable charge-domain switched-g[subscript m]-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge sharing technique. It uses only switches, capacitors, linearity-enhanced gm-stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and -3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two proposed biquads in a 65nm LPE CMOS process. A tunable center frequency of 35−70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies a core area of 0.17mm². In the second part, a highly linear continuous-time low-pass filter (LPF) topology with source follower coupling is presented that achieves excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two proposed filter stages in a 0.18μm CMOS, and occupies a core area of 0.12mm². Operating with a 1.3V supply voltage, the filter consumes only 0.5mA current, and achieves a -3dB bandwidth of 20MHz with 82dB stop-band rejection. A total harmonic distortion (THD) of -39.5dB at the output is measured with a +6.6dBm (i.e. 1.35V[subscript pk-pk]) input signal at 2MHz. The measured in-band IIP3 is +28.8dBm. The dynamic range (at 1% THD) is 76.8dB, with 15.3nV/√Hz averaged in-band input-referred noise. A pseudo-differential-VCO based 2nd-order continuous-time ΔΣ ADC with a residue self-coupling technique is proposed and implemented with mostly digital circuits in the third part. Two VCOs are arranged in a pseudo-differential manner. The digital output is obtained by comparing the sampled output phase of one VCO with that of the other. Passive subtraction is realized in current domain to obtain the residue at the VCO input. The residue self-coupling is implemented using a linear 1st-order transconductance low-pass filter (TCLPF). Moreover, a highly linear VCO topology is presented. The transistor-level simulations in a 65nm CMOS process show a 78dB SNDR over a 10MHz signal bandwidth with a power consumption of 2.9mW, which is 16dB improvement in contrast to the case with the TCLPF block powered off