8,044 research outputs found
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3- 182times for a Xilinx Virtex5 LX 330T, 1.3-33times for an IBM Cell, and 3-131times for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160 implementation for a variety of single-precision device models
Hand-arm vibration disorder among grass-cutter workers in Malaysia
Prolonged exposure to hand-transmitted vibration from grass-cutting machines has been associated with increasing occurrences of symptoms and signs of occupational diseases related to hand-arm vibration syndrome (HAVS). Methods. A cross-sectional study was carried out using an adopted HAVS questionnaire on hand-arm vibration exposure and symptoms distributed to 168 male workers from the grass and turf maintenance industry who use hand-held grass-cutting machines as part of their work. The prevalence ratio and symptom correlation to HAVS between high and lowâmoderate exposure risk groups were evaluated. Results. There were positive HAVS symptoms relationships between the lowâmoderate exposure group and the high exposure group among hand-held grass-cutting workers. The prevalence ratio was considered high because there were indicators that fingers turned white and felt numb, 3.63, 95% CI [1.41, 9.39] and 4.24, 95% CI [2.18, 8.27], respectively. Less than 14.3% of workers stated that they were aware of the occupational hand-arm vibration, and it seemed to be related to the finger blanching and numbness. Conclusion. The results suggest that HAVS is under-diagnosed in Malaysia, especially in the agricultural sectors. More information related to safety and health awareness programmes for HAVS exposure is required among hand-held grass-cutting workers
Si/Ge hole-tunneling double-barrier resonant tunneling diodes formed on sputtered flat Ge layers
We have demonstrated Si/Ge hole-tunneling double-barrier resonant tunneling diodes (RTDs) formed on flat Ge layers with a relaxation rate of 89% by our proposed method; in this method, the flat Ge layers can be directly formed on highly B-doped Si(001) substrates using our proposed sputter epitaxy method. The RTDs exhibit clear negative differential resistance effects in the static currentâvoltage (IâV) curves at room temperature. The quantized energy level estimation suggests that resonance peaks that appeared in the IâV curves are attributed to hole tunneling through the first heavy- and light-hole energy levels
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
Automatic transistor sizing is a challenging problem in circuit design due to
the large design space, complex performance trade-offs, and fast technological
advancements. Although there has been plenty of work on transistor sizing
targeting on one circuit, limited research has been done on transferring the
knowledge from one circuit to another to reduce the re-design overhead. In this
paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning
(RL) to transfer the knowledge between different technology nodes and
topologies. Moreover, inspired by the simple fact that circuit is a graph, we
learn on the circuit topology representation with graph convolutional neural
networks (GCN). The GCN-RL agent extracts features of the topology graph whose
vertices are transistors, edges are wires. Our learning-based optimization
consistently achieves the highest Figures of Merit (FoM) on four different
circuits compared with conventional black-box optimization methods (Bayesian
Optimization, Evolutionary Algorithms), random search, and human expert
designs. Experiments on transfer learning between five technology nodes and two
circuit topologies demonstrate that RL with transfer learning can achieve much
higher FoMs than methods without knowledge transfer. Our transferable
optimization method makes transistor sizing and design porting more effective
and efficient.Comment: Accepted to the 57th Design Automation Conference (DAC 2020); 6
pages, 8 figure
Validating foundry technologies for extended mission profiles
This paper presents a process qualification and characterization strategy that can extend the foundry process reliability potential to meet specific automotive mission profile requirements. In this case study, data and analyses are provided that lead to sufficient confidence for pushing the allowed mission profile envelope of a process towards more aggressive (automotive) applications.\ud
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Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band
Emerging health-monitor applications, such as information transmission
through multi-channel neural implants, image and video communication from
inside the body etc., calls for ultra-low active power (<50W) high
data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous
literature has strongly focused on low average power duty-cycled radios or low
power but low-date radios. In this paper, we investigate power performance
trade-off of each front-end component in a conventional radio including active
matching, down-conversion and RF/IF amplification and prioritize them based on
highest performance/energy metric. The analysis reveals 50 active
matching and RF gain is prohibitive for 50W power-budget. A mixer-first
architecture with an N-path mixer and a self-biased inverter based baseband
LNA, designed in TSMC 65nm technology show that sub 50W performance can
be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018
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