Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET

A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail

SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography

textA highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 μm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.Materials Science and Engineerin

Projecting productivity growth: lessons from the U.S. growth resurgence

Following the 1995-2000 period of more rapid output growth and lower inflation in the United States, economists have strenuously debated whether improvements in economic performance can be sustained. The recession that began in March 2001 intensified the debate, and the economic impacts of the events of September 11 have yet to be fully understood. Both factors add to the considerable uncertainties about future growth that currently face decision makers in both the public and private sectors. ; In this article, the authors analyze the sources of U.S. labor productivity growth in the post-1995 period and present projections for both output and labor productivity growth for the next decade. Despite the 2001 downward revisions to U.S. gross domestic product and software investment, the authors show that information technology (IT) played a substantial role in the U.S. productivity revival. The article then outlines a methodology for projecting trend output and productivity growth. The base-case projection puts the rate of trend productivity growth at 2.21 percent per year over the next decade with a range of 1.33 to 2.92 percent, reflecting fundamental uncertainties about the rate of technological progress in IT-production and investment patterns. The central projection is only slightly below the average growth rate of 2.36 percent during the 1995-2000 period.Productivity ; Technology ; Economic development

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Projecting Productivity Growth: Lessons from the U.S. Growth Resurgence

This paper analyzes the sources of U.S. labor productivity growth in the post-1995 period and presents projections for both output and labor productivity growth for the next decade. Despite the recent downward revisions to U.S. GDP and software investment, we show that information technology (IT) played a substantial role in the U.S. productivity revival. We then outline a methodology for projecting trend output and productivity growth. Our base-case projection puts the rate of trend productivity growth at 2.21% per year over the next decade with a range of 1.33 - 2.92%, reflecting fundamental uncertainties about the rate of technological progress in IT-production and investment patterns. Our central projection is only slightly below the average growth rate of 2.36% during the 1995-2000 period.productivity, information technology

Roadmap on semiconductor-cell biointerfaces.

This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world

An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper