16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell

International audienceThis paper presents for the first time a TFET/CMOS hybrid CAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications like the IoT (Internet of Things). Proposed design is low power, area efficient and re-configurable i.e. can either be used as CAM or normal SRAM or as a combination of both. The simulation extractions for power and speed are done including wiring and device parasitic capacitances from 16Kb CAM designed in 28nm FDSOI CMOS process using MOSFETs and Tunnel FETs (TFETs). The proposed CAM architecture supports voltage scaling and allows application of performance boosting techniques without impacting cell leakage. Less than 5 fA/bit memory array leakage current is achieved at 1V supply voltage, showing up-to 106× improvement compared with state-of-the-art CMOS SRAM and CAM bitcells, respectively. Minimum write access pulse for CAM and SRAM mode is 1.37ns evaluated at 1V supply voltage. Evaluated access pulse is 1.39ns and 1.03ns for CAM and SRAM mode reads, respectively at 1V