A Flexible Open-Source Framework for FPGA-based Network-Attached Accelerators using SpinalHDL

Abstract

Domain-specific accelerators are increasingly vital in heterogeneous computing systems, driven by the demand for higher computational capacity and especially energy efficiency. Network-attached FPGAs promise a scalable and flexible alternative to closely coupled FPGAs for integrating accelerators into computing environments. While the advantages of specialized hardware implementations are apparent, traditional hardware development and integration remain time-consuming and complex. We present an open-source framework which combines a hardware shell with supporting software libraries, which enables fast development and deployment of FPGA-based network-attached accelerators. In contrast to traditional approaches using VHDL or Verilog, we leverage generative programming with SpinalHDL, providing a flexible hardware description with multi-level abstractions. This work eases the integration of accelerators into existing network infrastructures and simplifies adaptation to different FPGAs, eliminating complex and lengthy top-level hardware descriptions