Formulation and Mitigation of Soft Error in CMOS Memory System by using Transmission Gate

Abstract

The downscaling of technology has resulted in increased packing density in CMOS technology and thus, a worrying uptick in single event upset susceptibility in contemporary technology. SRAMs in particular, which now occupy up to 70% of all chip size, are vulnerable to errors from single event upsets, leaving the reliability of its memory storage potentially compromised. The application of submicron electronics in areas of high particle activity in fields such as aerospace calls for the need for technology that is resistant against the occurrence of soft errors, with an increased capacity of mitigating the phenomenon of single event upsets. The current literature has proposed methods such as radiation hardening through methods such as transistor sizing and triple modular redundancy which are unable to keep pace with technology downscaling. This study aims to characterize and model the transient pulse formed from a single event upset, formulate the probability of a state flip in various SRAMs, and produce a transient filter based on transmission gate. The transient pulse, modelled by the double exponential model is injected into the vulnerable memory nodes of the interlocked inverters, Q and QB in the 4T, 6T and 9T SRAMs to observe the amplitude of transient pulse required to incite a state change. The critical charge is then calculated from the readings, and its subsequent probability is calculated further based on the memory node area, technology node of 180nm and the atmospheric cross section per unit area constant. The transmission gate transient filter SRAM achieves an 88% improvement in error probability reduction