Innovative gate driver structure achieving low jitter across isolation barrier for parallel connected SiC modules

Abstract

International audienceThe parallel connection of power transistors is a common approach to enhance the current capability ofconverter systems. However, the development of wide bandgap semiconductors introduces significantchallenges in parallel operation, primarily due to the need to synchronize sharp current edges duringswitching. One cause of current imbalance is the delay between gate signals resulting from mismatches ingate drivers. This article presents a novel structure designed to ensure synchronization of eight gate driversfor SiC modules in parallel while addressing the issue of gate loop oscillation. Rigorous measurements areconducted to investigate the performances of a low-jitter isolation barrier and the gate driver's behaviourunder different temperatures. Additionally, part-to-part variations among four gate drivers were examined.The results demonstrate a jitter below 2 ns on the parallel gate voltage, highlighting the effectiveness of theproposed solution