On the design of continuous-time incremental delta-sigma modulators

Abstract

Incremental delta-sigma analog-to-digital converters (ADCs) have not been as widely recognized as their free-running counterparts over the last few decades. However, recently, they have been gaining more attention due to their ability to fill a long-existing gap in the field. Highly robust oversampling and noise-shaping ADCs are not capable of providing a sample-by-sample conversion at Nyquist-rate, which is a crucial requirement for several applications such as multiplexing on single-shot conversion. Incremental ADCs have the capability to address this requirement. However, in order to compete with the well-established choice of true-Nyquist rate converters such as non-noise-shaped successive-approximation register (SAR) ADCs, incremental converters must exhibit competitive robustness and efficiency while also pushing their boundaries to higher conversion speeds. Until now, incremental converters have primarily been used for low or moderate bandwidths. While discrete-time architectures have been widely used in the state-of-the-art of incremental delta-sigma ADCs, this particular work focuses on continuous-time incremental converters. The goal is to promote the attractive idea of a Nyquist-rate ADC with a resistive input and establish a strong foundation for future designs with higher bandwidths ranging from tens to hundreds of MHz. This thesis showcases the successful manufacturing of two prototypes that further expand the bandwidths of incremental ADCs and represent the current state-of-the-art. The design process and challenges faced during development, along with the solutions introduced, are also highlighted. Both prototypes are calibration-free and maintain a resolution above 13 bits with exceptional linearity. The first prototype is implemented in a 180-nm CMOS process, while the second one is implemented in a more advanced 28-nm CMOS proces