Modelling noise and delay in VLSI circuits.

Pamunuwa, Dinesh B.; Elassaad, S.; Tenhunen, H.

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oai:eprints.lancs.ac.uk:31101

Modelling noise and delay in VLSI circuits.

Authors: Dinesh B. Pamunuwa
S. Elassaad
H. Tenhunen
Publication date: 1 February 2003
Publisher
Doi

Abstract

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay

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