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VHDL Design of Advanced CPU

By Daniel Slavík

Abstract

The goal of this project was to study pipelined processor architectures along with instruction and data cache. Chosen pipelined architecture should be designed and implemented using VHDL language. Firstly, I decided to implement the subscalar architecture first, secondly, three versions of scalar architecture. For these architectures synthesis into FPGA was done and performance of these architectures was compared on chosen algorithm. In the next part of this thesis I designed and implemented instruction and data cache logic for both architectures. However I was not able to synthetise these caches. Last chapter of this thesis deals with the superscalar architecture, which is the architecture of nowadays

Topics: návrh; RAM; procesor; VHDL; superskalární; cache; scalar; skalární; design; superscalar; subskalární; processor; subscalar
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Year: 2010
OAI identifier: oai:invenio.nusl.cz:237134
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