Shape-oriented test set compression method using ideal vector sorting and shapes


This thesis details a novel shape-oriented test set compression method that offers an alternative approach to reduce large test data of a complex circuit under test (CUT) such as the system-on-a-chip (SoC). Rather than the usual one-dimensional compression approach utilized by other contemporary compression techniques, such as the Huffman coding and Lempel-Ziv-Welch (LZW) method, the proposed method compresses a test set in a two-dimensional style. To achieve the compression, the proposed method initially sorts test cubes, which are sent to the combinational CUT to detect the single stuck-at faults of the chip, by employing the ideal vector sorting algorithm; the algorithm rearranges cubes based on the test data that resemble parts of predefined shapes identified in the cubes. After the cubes are sorted, the amalgamated-shapes area-covering algorithm of the proposed method attempts to discover predefined shapes or blocks and stores the corresponding information. In the last stage of the proposed method, the multi-syntax encoding algorithm converts the stored information into encoding bits. The experimental results show that the proposed method has higher compression ratios compared to that of other contemporary compression schemes in most cases. As a result, compared to other schemes, employing the shape-oriented method can lessen the time of transferring and can reduce the memory for storing the compressed data further.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat

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Last time updated on 14/12/2019

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