Includes bibliographical references.Optical switches based on GaAs/AlGaAs vertical-cavity surface-emitting lasers and heterojunction phototransistors are combined monolithically into new switching configurations that perform optical logic and spatial routing in a dynamically programmable manner. Using simple voltage control, many different logic and routing configurations, including AND and OR gates with variable fan-out, can be implemented using the same hardware.The work at UNM was supported by AFOSR (Bolling AFB), ARPA, and Rome Labs (Griffiss AFB). The Sandia effort was supported by DOE Contract No. DE-AC04-94AL85000

Adams, A. C.

Chalmers, S. A.

Cheng, Julian

Lear, Kevin L.

Leibenguth, Richard E.

Lu, Bo

Lu, Yin-Chen

Vawter, G. A.

Zhou, Ping

Zilko, John Leon

Zolper, J. C.

English

Optical switches based on GaAs/AlGaAs vertical-cavity surface-emitting lasers and heterojunction phototransistors are combined monolithically into new switching configurations that perform optical logic and spatial routing in a dynamically programmable manner. Using simple voltage control, many different logic and routing configurations, including AND and OR gates with variable fan-out, can be implemented using the same hardware.The work at UNM was supported by AFOSR (Bolling AFB), ARPA, and Rome Labs (Griffiss AFB). The Sandia effort was supported by DOE Contract No. DE-AC04-94AL85000

Vawter, G. A., author

Chalmers, S. A., author

Zolper, J. C., author

Lear, Kevin L., author

Zilko, John Leon, author

Adams, A. C., author

Leibenguth, Richard E., author

Cheng, Julian, author

Lu, Yin-Chen, author

Zhou, Ping, author

Lu, Bo, author

IEEE, publisher

Mountain Scholar (Digital Collections of Colorado and Wyoming)

398 IEEE PHOTONICS TECHNOLOGY LEITERS, VOL. 6, NO.3, MARCH 1994Binary Optical Switch and ProgrammableOptical Logic Gate Based on the Integrationof GaAsIAIGaAs Surface-Emitting Lasersand Heterojunction PhototransistorsBo Lu, Ping Zhou, Yin-Chen Lu, Julian Cheng, Senior Member, IEEE, R. E. Leibenguth, A. C. Adams, J. L.Zilko, K. L. Lear, J. C. Zolper, Member, IEEE, S. A. Chalmers and G. A. Vawter, Member, IEEEAbstract- Optical switches based on GaAslAlGaAs vertical-cavity surface-emitting lasers and heterojunction phototransistorsare combined monolithically into new switching configurationsthat perform optical logic and spatial routing in a dynamicallyprogrammable manner. Using simple voltage control, many dif-ferent logic and routing configurations, including AND and ORgates with variable fan-out, can be implemented using the samehardware.I. INTRODUCTIONW E DESCRIBE the first experimental demonstration ofa novel optical switch that can be dynamically recon-figured to perform both optical logic and the spatial routingfunctions, thus providing the basis for functionally flexible,programmable optical logic architectures. The technology isbased on the monolithic integration of vertical-cavity surface-emitting lasers (VCSELs) and heterojunction phototransistors(HPTs) or photothyristors (PNPNs) to form a new class of two-dimensional binary optical switch nodes which, in addition tologic and routing, also possess reconfigurability and a fan-outcapability. Efficient VCSEL-based optical switches have beendescribed previously, [IJ, [2J and single-stage optical logicgates based on latching PNPNNCSEL switches [IJ and non-latching HPTNCSEL switches [1]-[3J have demonstrated thebasic Boolean functions-AND, OR, INVERT, NAND, NOR,and XOR. More complex Boolean functions can be derivedby optically cascading sequential logic gate arrays, whichrequires critical optical packaging. This can be minimizedby reconfiguring a programmable logic gate array after eachprocessing cycle in conjunction with an optical buffer memory,[1] so that a single logic array can be used repeatably to sim-plify both the optical and optoelectronic hardware. To applythis minimalist approach to arbitrary optical logic functionsrequires a greater level of integration and programming ofthe spatial routing [4J and logic functions. We will showManuscript received November 10, 1993; revised December 23, 1993.B. Lu, P. Zhou, Y.-C. Lu and 1. Cheng are with the University of NewMexico, Center for High Technology Materials, Albuquerque, NM 87131.R. E. Leibenguth, A. C. Adams, and J. L. Zilko are with AT&T BellLaboratories Breinigsville, PA 18031.K. L. Lear, J. C. Zolper, S. A. Chalmers and G. A. Vawter are with theSandia National Laboratory, Albuquerque, NM 87185.IEEE Log Number 9216576.below that our new optoelectronic switching technology cancombine the functions of routing, logic, and fan-out in a single,dynamically programmable switching fabric.The designs of the 1 x 2 and 2 x 2 binary optical switch,plus their principal modes of logic and routing operations,are shown in Fig. 1. The optical input port contains twonearly contiguous but electrically-isolated HPT segments, eachcontrolled by a separate bias voltage (V, or l!2) and eachserially connected to a different VCSEL output port. Opticalinput data impinge upon both segments in equal proportions,and depending on the state of (V" V2 ) , which can be either ONor OFF, the photoinduced and amplified current from the HPTis routed alternatively to VCSEL #1 (1,0), to VCSEL #2 (0,1), or to both veSELs (1, 1), where the data is regeneratedas an amplified optical output. Thus alternate routing as wellas an optical fan-out of 2 can be achieved.The 2 x 2 switch consists of two 1 x 2 switches thatconcatenate two nodes each containing a segmented HPT and aVCSEL. Every HPT is connected to two veSELs (at least oneof which is associated with another node), and the VeSEL ateach node is similarly connected to two HPTs at different sites.The in-plane interconnection of nodes functionally defines alogic or a spatial routing function. Two nodes may share onlyone (e.g., Omega network) or both (e.g., Banyan network)input and output ports, depending on the routing networktopology. Routing is controlled by the states of the voltages(V" V2 ) and (V~, VD, which provide a larger number of routingconfigurations, including the important bypass (1, 0, 0, 1) andexchange (0, 1, 1, 0) operations [4J. A reconfigurable multi-stage switching network can be realized by optically cascadingarrays of suitably interconnected 2 x 2 switches, [4] whichdefine a specific routing topology with surface-normal opticalinputs and outputs.The VeSEL at each node is connected to two HPTs fromdifferent nodes and thus sums the amplified photocurrentsgenerated by optical inputs A and B . Since the VeSEL isa thresholding device, these sums can determine the logicoutcome A-OR-B (A+B) or A-AND-B (A·B), depending onwhether the two optical inputs can individually or collectivelyproduce a sufficient current to switch on the VeSEL. Bycontrolling the prebias or the threshold of each switch, either1041-1135/94$04.00 © 1994 IEEELU et al.: BINARY OPTICAL SWITCH AND PROGRAMMABLE OPTICAL LOGIC GATE 3991 0 1 0(b)1 1 1 11 1 1 0(d)Fig. 1. The design and operating principles of a 2 x 2 binary optical switch, showing the logic configurations (a) (1, 0, I, 0), (b) (1, I, I, I), and(c) (1, I, 1, 0) with variable fan-out. The monolithic layout of the switch is shown in (d). Depending on the optical input signal and bias levels, eitherA-OR-B logic or A-AND-B logic can be implemented.AND or OR logic operation can be realized, and the opticallyamplified logic output can emerge from either or both VC-SELs. The control voltages (VI, V2 , V2,Vi) completely specifythe logic and routing functions of the switch. When eitherVi = V{ or V2 = V2 is activated (Fig. la), the optical logicoutput emerges from port A (I, 0, I, 0) or port B (0, 1, 0,I), respectively, with a fan-out of 1. When both nodes are inthe ON-state (1, 1, I, 1), the logic output emerges from bothports with a fan-out of 2 (Fig. I(b)). In the (I, I, I, 0) or the(0, 1, I, 1) configuration (Fig. I(c)), the logic output emergesfrom one of the output ports, while A or B is routed to theother. The 2 x 2 switch thus performs the binary optical logicfunctions (A . B) and (A +B), and routes the output to eitheror both output ports, with all the controls provided by a setof control voltages.The binary switch, whose detailed structure and fabricationare described elsewhere [5], consists of an n-p-n GaAsIAIGaAsHPT structure (emitter-up configuration) that is epitaxially re-grown on a top-surface-emitting GaAs/AIGaAs VCSEL struc-ture (lasing wavelength ~ 850 nm) by molecular beam epitaxy(MBE), and the two are electrically isolated by an undopedGaAs layer. The monolithic 2 x 2 switch layout (Fig. I(d))shows two segmented HPT input ports and two VCSEL outputports, with counter-propagating optical inputs and outputsoccurring at the same (epitaxial) surface. The active area (20J1m diameter) of each VCSEL is defined by a single 335 keVproton implant, and all the VCSELs and HPTs are electricallyisolated by a multiple-energy, multiple-dose proton implant.The HPT segments at each node are isolated by a narrowetched trench. The threshold of the VCSELs is 4-6 rnA, theirslope efficiency Tis is between 30-60%, and the optical currentgain (3 of the HPTs ranges from 70 to 100.To demonstrate the logic operation of the HPTNCSELswitch, input optical data containing a dc and a pulsed com-ponent is incident on both HPT segments. The de intensityis adjusted so that the amplified photocurrent prebiases theVCSEL below threshold, while the pulsed optical logic inputsthen singly or collectively bring the VCSEL above threshold toproduce a logic output. Taking into account various systemiclosses (~ 75%), a total input intensity of ~ 500 J1W, including400 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 6, NO.3, MARCH 1994Fig. 2. Experimental demonstration of the optical logic functions (a) A +B,and (b)A . B, using the a 2 x 2 optical switch operating in the (I, 0, 1, 0)configuration.(3 ~ 100, and the VeSELs have a threshold of 4 mA. Anotherlogic configuration that further demonstrates the flexibility ofthe 2 x 2 switch is the (1, 1, 1, 0) mode shown in Fig. l(c)and experimentally demonstrated in Fig. 4(a), in which thelogic output (A +B) or (A· B) emerges from one output port(VeSEL #1), while A or B is routed to the other (VeSEL #2)under the control of the routing voltage pulses. Here A andB are two continuous pulse trains with different frequenciesand amplitudes. Output channel 1 contains only the pulsesof A, while output channel 2 contain the pulses of both Aand B, which are logically summed. Note that the (1, 1,1, 0) and (1, 0, 1, 0) configurations are logically identical,differing only in the presence of the control voltage V2, whichcauses a second photocurrent fA to be generated and routedto VeSEL #2 to produce a replica of the input A. Since thetwo segments of each HPT are electrically isolated, neither V2nor the photocurrent that it produced can affect the operationof the remaining logic function, which is otherwise identicalto that of the (1, 0, 1, 0) case.Fig. 4(b) shows the optical response of the HPTNeSELswitch to an optical input pulse (20 ns wide) with a sub-threshold de optical prebias. The rise time of the output pulseis ~ 3 ns, but its pulse width (~ 15 ns) appears to be narrowerthan that of the input pulse. The switching speed is governedmainly by the fall time of the HPT, which is quite long due toits large area (40 JLm x 80 JLm). But since lasing ceases as soonas the collector current falls below threshold, this occurs in atime (~ 15 ns) shorter than that required to fully dischargethe junctions to their sub-threshold prebias level (~ 20 ns).AND GatelOOnsldiv(a) ORGate100-200 JLW for the data pulses, is needed to bring the VeSELabove threshold to a region of high slope efficiency.The 2 x I mode of operation (logic with a fan-out ofI) is selected by setting the (pulsed) control voltages of the2 x 2 switch for the (1, 0, 1, 0) configuration (Fig. l(a)).The amplitude of these voltages (5.5 V), chosen to bias theVeSEL above threshold (2.3 V) and to bias the HPTs in thegain region (2 V), is also partly distributed across the seriesresistance of the VeSEL (~ 100 n). The inputs A and B aresynchronous optical pulse patterns (850 nm, 10 MHz, 3D-50ns pulse width) that are incident on the HPTs in channels1 and 2, respectively. In the (1, 0, 1, 0) configuration, theiramplified photocurrents are routed to and summed by VeSEL# 1. By adjusting the de components of A and B to prebias theVeSEL at different levels below threshold (100 JLW each forA+B, and 0 JLW for A· B), the pulsed logic inputs of A and B(200 JLW) can then either individually or collectively drive theVeSEL above threshold to produce the amplified optical logicoutputs (A +B) and (A· B), respectively. In the experimentaldemonstration of (A + B) logic in Fig. 2(a), VeSEL # 1 isswitched on whenever pulses appear in either or both inputs Aand B (total power ~ 550 JLW). The logic output can emergefrom either channell or channels 2 by selecting the (1, 0,1, 0) or (0, 1, 0, 1) configuration, respectively. When pulsesare present in both A and B, the larger summed photocurrentdrives the VeSEL further above threshold, thus producing ahigher output power (250 JLW average) than when only A orB is present. This is not a serious defect for cascaded OR-gateoperation, since switching can be effected by any optical signalexceeding an optical threshold. However, it does broaden theoptical output pulse, since the HPT must disccharge furtherbefore its collector current falls below the VeSEL threshold.Part of the broadening is also due to differences in the chargingdelays in the HPT associated with the individual photocurrentsproduced by A and B, which may not be exactly the same dueto differences in optical coupling into the HPT. Both of theseeffects can be substantially reduced by improved design.By removing the de bias, the amplitudes of the pulses inA or B alone no longer have sufficient intensity to switchon the VeSEL (1 + 0 = 0 + 1 = 0). Only when pulsesare present in both A and B will sufficient photocurrent begenerated to collectively bring the VeSEL above threshold(1 + 1 = 1). The (A . B) logic operation is demonstrated inFig. 2(b), using 200 JLW pulses (50 ns wide) without a deprebias. The total power incident on A and B is thus 400 JLW,and the average output power of the VeSEL is 100 JLW. Theexpected optical gain (G ~ 5) based on the values of (3and 1)8is not observed, due largely to gain compression in the HPTat above-threshold current densities. With improvements in 1)8and (3, a much higher optical gain can be achieved to facilitatethe optically cascaded operation of multi-stage switching orsequential optical logic.Logic operations (A . B) and (A . B) with a fan-out oftwo are experimentally demonstrated in Figs. 3(a) and 3(b),respectively, using a 2 x 2 switch operating in the (1, 1,1, 1) configuration (Fig. l(b)).The logic outputs, which arequalitatively similar to those of Fig. 2, now emerge fromboth output channels (fan-out of 2). For these experiments,LU et al.: BINARY OPTICAL SWITCH AND PROGRAMMABLE OPTICAL LOGIC GATE 401(a)AOR Gate1JlS/div(b) ANDGateSOOnsldivAInputCR.!InputCR. 2OutputCR.!OutputCR. 2•AB(a)CR.1S~divOutputPulse(b)20ns/divFig. 3. Experimental demonstration of the logic function (a) A + B, and(b) A . B, with an optical fan-out of two, using a 2 x 2 switch operating inthe (1, 1, 1, 1) configuration.This differs from Fig. 2, in which the optical output pulse isbroadened, in two ways. First, the VCSEL is driven not asfar above threshold and thus the HPT needs not discharge asmuch, and second, there is no differential charging delay sincea single optical input is used. Logic operations at 20-50 Mb/scan be achieved using the present devices, and by reducingthe HPT size, improving f3 and 'r/s, a switching speed in thehundreds of Mb/s range is possible.In conclusion, we have described the design and experimen-tal demonstration of a reconfigurable binary optical switch thatcan perform optical routing and logic functions in many dif-ferent spatial configurations. By combining logic and routingin a single programmable switching fabric, we have a potentialtechnology for a programmable optical logic gate array.ACKNOWLEDGMENTThe work at UNM was supported by AFOSR (BollingAFB), ARPA, and Rome Labs (Griffiss AFB). The San-dia effort was supported by DOE Contract No. DE-AC04-Fig. 4. (a) Experimental demonstration of the (1, 1, 1, 0) configuration,showing the routing of logic output (A + B) to channell, and the input Ato channel 2, under pulsed control voltages (which ended before the last twodata pulses of A). (b) The optical response of a single element of the 2x2switch with a sub-threshold prebias to a 20-ns wide optical pulse incident ona single HPT.94AL85000. We gratefully acknowledge the technical assis-tance of J. Escobedo of Sandia Labs.REFERENCES[1] J. Cheng and P. Zhou, "Integrable surface-emitting laser-based opti-cal switches and logic gates for parallel digital optical computing,"Appl. Opt., Special Issue on Optical Computing, vol. 31, no. 26, pp.5592-5603, 1992.[2] W. K. Chan, [30] W. K. Chan, J. P. Harbison, A. C. von Lehmen,L. T. Florez, C. K. Nguyen and S. A. Schwarz, "Optically-controlledsurface-emitting lasers," Appl. Phys. Lett. vol. 58, pp. 2342-44, May1991.[3] Y. H. Lee, et. al., "Active optical NOR logic devices using surface-emitting lasers," IEEE Photon. Technol. Lett., vol. 4, pp. 479-482,1992.[4] J. Cheng, P. Zhou, S. Z. Sun and D. R. Myers, "Surface-emitting laser-based smart pixels for two-dimensional optical logic and reconfigurableoptical interconnections," IEEE J. of' Quantum Electron., vol. 29, no. 2,pp. 741-756, Special issue on Smart Pixels.[5] P. Zhou and 1. Cheng, et. al., "Monolithic optotelectronic switchbased on the integration of a GaAs/AlGaAs heterojunction bipolartransistor and a GaAs vertical-cavity surface-emitting laser," IEEEPhoton. Technol. Lett., vol. 5, pp. 1035-1038, 1993.

Binary optical switch and programmable optical logic gate based on the integration of GaAs/AlGaAs surface-emitting lasers and heterojunction phototransistors

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Binary optical switch and programmable optical logic gate based on the integration of GaAs/AlGaAs surface-emitting lasers and heterojunction phototransistors

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