Network adapter architectures in network on chip: comprehensive literature review

Abstract

Network on Chip (NoC) is a new distributed, scalable, packet switched-based on chip which has been suggested as perfect solution for traditional centralized, non-scalable bus-based systems on chip (SoC) to handle issues like out-of order transactions, higher latencies, and end-to-end flow control. The NoC provides parallel and multi-core processing platform and is constructed from a set of Routers (R), Links (L), Intellectual Property (IP) cores, and Network Adapters (NA). The NA as individual hardware entity makes it possible IP cores with different data width and frequency connected to NoC. In other words, by decoupling computation from communication the NA allows IP Core modules and interconnects to be designed independently from each other. The design of NA impacts directly on NoC based SoCs critical parameters such as power dissipation, latency, throughput, and silicon area. This paper presents the comprehensive review of state-of-the-art architectures and the developments of NA which have been proposed in literature. Moreover, three type of parameters namely design (design goal, building components, Quality of Service (QoS), Core Interface Protocol (CIP), Security consideration, and Design for Test (DfT)), performance (power dissipation, latency, area, and throughput), and evaluation parameters (evaluation platform, clock frequency, technology scale) which have impact on NA architectures are evaluated and highlighted in comparative tables and figures. Furthermore, all the concepts that are considered in the design of NA is classified. Finally, concluding remarks and future research direction are provided. © 2019, Springer Science+Business Media, LLC, part of Springer Nature