'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
This paper describes a method for analyzing and
predicting the timing properties of a program fragment.
The paper first presents a little language implemented to
describe a processor’s architecture and a static WCET
estimation method is then presented. The timing analysis
starts by compiling a processor’s architecture program
followed by the disassembling of the program fragment.
The assembler program is then decomposed into basic
blocks and a call graph is generated. These data are later
used to evaluate the pipeline hazards and cache miss that
penalize the real-time performance. Finally, some
experimental results of using the developed tool to predict
the WCET of code segments with some Intel
microcontroller are presented.
execution, the desired time will be found by
averaging. Even with this approach, if you want
an accurate measurement, a number of
complications such as, compiler optimizations,
operating system distortions, must be solved.
Nevertheless, these approaches are unrealistic since
they ignore the system interferences and the effects of
cache and pipeline, two very important features of some
processors that can be used in our hardware architecture.
Shaw [1], Puschner [2], and Mok [3], developed some
very elaborated methodology for WCET estimation, but
none of them takes into account the effects of cache an