A new TDC-chip is under development for the COMPASS experiment at CERN. The
ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow
high resolution time measurements with digitization of 75 ps, and an
unprecedented degree of flexibility accompanied by high rate capability and low
power consumption. Preliminary specifications of this new TDC chip are
presented.
  Furthermore a FPGA based readout-driver and buffer-module as an interface
between the front-end of the COMPASS detector systems and an optical S-LINK is
in development. The same module serves also as remote fan-out for the COMPASS
trigger distribution and time synchronization system. This readout-driver
monitors the trigger and data flow to and from front-ends. In addition, a
specific data buffer structure and sophisticated data flow control is used to
pursue local pre-event building. At start-up the module controls all necessary
front-end initializations.Comment: 5 pages, 4 figure

Braun, G.

Fischer, H.

Franz, J.

Grunemaier, A.

Heinsius, F. H.

Konigsmann, K.

Schierloh, M.

Schmidt, T.

Schmitt, H.

Urban, H. J.

English

arXiv

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented degree of flexibility accompanied by high rate capability and low power consumption. Preliminary specifications of this new TDC chip are presented. Furthermore a FPGA based readout-driver and buffer-module as an interface between the front-end of the COMPASS detector systems and an optical S-LINK is in development. The same module serves also as remote fan-out for the COMPASS trigger distribution and time synchronization system. This readout-driver monitors the trigger and data flow to and from front-ends. In addition, a specific data buffer structure and sophisticated data flow control is used to pursue local pre-event building. At start-up the module controls all necessary front-end initializations.A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented degree of flexibility accompanied by high rate capability and low power consumption. Preliminary specifications of this new TDC chip are presented. Furthermore a FPGA based readout-driver and buffer-module as an interface between the front-end of the COMPASS detector systems and an optical S-LINK is in development. The same module serves also as remote fan-out for the COMPASS trigger distribution and time synchronization system. This readout-driver monitors the trigger and data flow to and from front-ends. In addition, a specific data buffer structure and sophisticated data flow control is used to pursue local pre-event building. At start-up the module controls all necessary front-end initializations

Heinsius, F.H.

Konigsmann, Kay

Urban, H.J.

CERN Document Server

arXiv:hep-ex/9810048v1  30 Oct 1998TDC Chip and Readout Driver Developmentsfor COMPASS and LHC-ExperimentsG. Braun, H. Fischer∗, J. Franz, A. Gru¨nemaier, F.H. Heinsius, K. Ko¨nigsmann,M. Schierloh, T. Schmidt, H. Schmitt, H.J. UrbanUniversita¨t Freiburg,Fakulta¨t fu¨r Physik, Hermann-Herder-Str. 3, D-79104 Freiburg, Germany∗EMAIL: Horst.Fischer@cern.chContribution to:fourth workshop on electronics for LHC experiments - LEB98Rome, 21-25 September 1998.AbstractA new TDC-chip is under development for the COMPASSexperiment at CERN. The ASIC, which exploits the 0.6µmCMOS sea-of-gate technology, will allow high resolutiontime measurements with digitization of 75 ps, and an un-precedented degree of flexibility accompanied by high ratecapability and low power consumption. Preliminary speci-fications of this new TDC chip are presented.Furthermore a FPGA based readout-driver and buffer-module as an interface between the front-end of the COM-PASS detector systems and an optical S-LINK is in devel-opment. The same module serves also as remote fan-outfor the COMPASS trigger distribution and time synchro-nization system. This readout-driver monitors the triggerand data flow to and from front-ends. In addition, a spe-cific data buffer structure and sophisticated data flow con-trol is used to pursue local pre-event building. At start-upthe module controls all necessary front-end initializations.1 INTRODUCTIONThe COMPASS experiment at CERN will investigatehadron structure by deep inelastic scattering processes andin addition pursue different aspects of hadron spectroscopyusing hadron beams. Comparison with calculations basedon operator product expansion or lattice techniques andwith model predictions based on chiral symmetry or effec-tive degrees of freedom will help to improve our under-standing of hadrons. To reach this objective a new state-of-the-art fixed target spectrometer, capable of standing beamintensities of up to 2 · 108 particles/spill and with excellentparticle identification, will be put into commission in theyear 2000.These challenging physics goals of the COMPASS Ex-periment can only be met, if at highest possible beam rateslarge data statistics can be recorded. This leads to therequirement of an experiment with negligible dead time,which can digest data rates of several Gigabyte per second.This is at the edge of today’s digitization and bandwidthtechnologies.The initial approach of the experiment was to mini-mize dead time by reading digitized data through pipelineswhere applicable. Availability of and resolution require-ments on digitization units have made this goal not feasi-ble for every detector component. The present scenario as-sumes a maximum dead time of 500 ns for analog sensitivefront-end electronics which will digitize signal amplitudeor charge with a precision better than 10 bit.The readout architecture of the COMPASS experimentis summarized in Figure 1. Data are digitized right at thedetector by the front-end electronics wherever possible. Incase of analog readout the pedestal subtraction and zerosuppression is performed by the front-end at the detector.To suppress background for time measurements only thosehits are transfered to the data recording units which have acorrelation to a trigger time.Filter Filter Filter Filter Filter Filter16x16 HippI SwitchROBROBROBROBDSPCATCHCentralDataRecordingHPPICPUHPPICPUHPPICPUHPPICPUi i i i. . . . . . . . . . . . FE-boards1. . . 16(on chamber)(9U VME)S-LinksTCSHIPPIROBsmax. 30 MB/s/linkmax. 100 MB/s/linkmax. 100 MB/s/linkSATAPV 6LATASD8bF1 TDCCalorimeterQVCRICHGASSIPLEXFigure 1: The architecture of the COMPASS detector read-out.The data are transmitted from the front-end to CATCHmodules (CATCH = COMPASS Accumulate, Transfer andCache Hardware). The functionality of the CATCH will bedescribed below.From the CATCH data are transmitted via a standardizedlink to the read-out buffers (ROB) which can store all datafrom one spill. The backbone of this data transfer is theS-link [1] interface and the S-LINK data transfer protocol.Presently about 128 S-LINK connections are foreseen totransmit data with a maximum total bandwidth of about12 GB/s.The read-out buffers combine data which belong to oneevent, check consistency of the data and perform sub-event-building. In a next step they transmit the sub-events viaHiPPI [2] or Gigabit Ethernet to filter computers. Herethe final event-building is performed and events are re-constructed. The filter farm will reduce the data based onphysics cuts by a factor of 5 to 10 and a continuous rate of12 to 24 MB/s will be transfered to the central data record-ing facilities at CERN.2 THE F1 TDC CHIPA key element in the experiment is a new developed deadtime free TDC chip, the F1. It will be used to digitizethe data from a large majority of detectors. Table 1 showsthat the required specifications vary significantly for theforeseen applications of the F1 chip. Certainly the mostchallenging demands are defined by the scintillating fiber(SCIFI) detectors. Count rates up to 6 MHz per channel andtime resolution better than 100 ps are on the edge of today’stechnology. When count rates and background become toohigh, existing limitations in bandwidth on data-links be-tween TDC and the data recording system require on-chipevent selection. Detector components like Plastic IarocciTubes (µ-Detector 1) or MWPC do not ask for precise tim-ing but require lowest cost/channel due to the large numberof channels involved. Thus multiplexed input is desirablefor this kind of detectors. We were forced to develop anew multi-purpose TDC Chip, because no integrated TDCcircuit is currently on the market with a sufficient degreeof integration and flexibility to fulfill all requirements ofCOMPASS. In spite of the short time available for the R&Dphase for COMPASS we decided to develop a TDC in col-laboration with acam [3], a recently founded German enter-prise specialized in the development of time measurementdevices and applications.The development of the F1 resulted in a highly pro-grammable eight channel TDC ASIC based on a low cost0.6µm CMOS sea-of-gates process. The reasons for onlyeight channels in a single chip are driven by financial con-siderations as well as physical limitations. Eight channelsin a chip optimize savings due to density on the die andcosts for bonding and chip package. In addition chip prizesdepend strongly on the number of produced chips and lesson the die surface. Hence 6000 chips with 8 channels areTable 1: Possible applications for the F1 TDC-chip in theCOMPASS experiment.detector channels time background eventresolution rate rate[ps] [kHz] [kHz]Straws 37000 1000 600 100µMega Chambers 15000 <500 <100 <100µ-Detector 1 9000 — 50 <1µ-Detector 2 3000 2000 130 <1MWPC 18000 — 600 100SCIFI 1280 320 600 6000Beam Scintillators 512 <100 600 6000Recoil-Detector 5000 <100 <100 <100Hodoscope 1200 <100 <100 <100more cost efficient than 1500 chips with 32 channels.The scheme utilized in the F1 avoids the use of high-speed clocks and shift registers and, therefore, results invery low power consumption. Signal propagation times ingate arrays have very large variations as a function of tem-perature and operation voltage. Furthermore signal propa-gation within gates have a spread strongly dependent on theproduction process. To overcome these disadvantages theF1 exploits a self calibrating method utilized by voltagecontrolled delay elements as part of an asymmetric oscilla-tor in a phase locked loop (PLL).An outline of the chip is shown in Fig. 2. Non-perspective displayed boxes - like trigger counter, PLL orinterface FIFO - refer to units which are shared between theeight channels, whereas the perspective displayed boxes -like hit buffer, trigger matching and readout buffer - indi-cate logic units in the chip which come eightfold and arenot shared between the channels.The preliminary specifications for the TDC are listed inTable 2. The F1 can be considered as a real multi-purposechip with very different modes of operation in terms of res-olution and functionality.In the standard mode the F1 is an eight channel TDCchip with a digitization uncertainty of 150 ps. When a lead-ing or trailing edge of a LVDS-signal [4] is present at oneof the channel inputs the time relative to the last reset ofthe TDC is derived from a PLL and a coarse counter. Thetime stamp is written into the hit buffer. When a TTL signaledge is present at the trigger input the time relative to thelast reset is measured for the trigger signal. In a next stepthe time stamps, which are stored in the hit buffer, are com-pared to the time stamp of the trigger time. Data within apre-set time window are accepted for readout and copied tothe output buffer. An 8 or alternatively 24 bit parallel bus isused for readout of the chip. The data bus can be operatedat a maximum frequency of 50 MHz.In the high resolution mode two channels are interleavedby 1/2 least significant bit (LSB) delay. Hence in this modethe F1 has four channels with a resolution of 75 ps and theTable 2: Preliminary technical description of the F1 basedon pre-layout simulations.Number of channels:4 for high resolution mode8 for standard resolution mode32 for pattern recognition modeTime bin size:75 ps for high resolution mode150 ps for standard operation mode5700 ps for pattern recognition modeReference-clock frequency:Between 500 kHz and 40 MHz(Clock is used for self calibration only)Differential non-linearity:Less than 0.05 LSB for high resolution modeLess than 0.2 LSB for standard modeIntegral non-linearity:Less than one time binVariation with temperature:Less than one time binDynamic range:16 bitsDouble pulse resolution:Typical 22 nsDigitization and readout dead time:NoneHit buffer size:32 measurements for high resolution mode16 measurements for standard mode16 measurements for pattern recognition modeOutput buffer size:8 measurementsReadout Interface:16 measurementsTrigger buffer size:4Power Supply:5.0 V, optional 3.3 V with reduced resolution30 mA - 80 mA, depending on trigger loadTemperature range:-40 to +85 degree centigradeHit input:LVDS or TTLPackage:160 PQFPreferencetime+--relative time(0 - 9,830,250 ps)16(0 - 9,830 ns)trigger time-4x11 4x6Reference reset+-+->1=(4)wiretime1616Vcc16Reference Clock1 2 3 17 18 19triggermatching4resetcountertimereference15 4 3 0wiretime+-currenttrigger timecurrentPLL1611 61111-1111 11triggercounter6(data hold 30 - 150 ns)+ 1/2 LSBnext channeldelay to16x16hitbuffer1712345678interface FIFOI/O interfaceDAC8 x 8register8x1716x2424 Bit   or   24 to 8 Bit124(i.e. 38.88 MHz)248 or 63output bufferTriggerTriggeroffsetTriggerwindowAD8842Setup dataEventnumberDataoutCommon startFigure 2: Outline of the F1 chip.hit buffer for a single channel is increased by a factor oftwo. Otherwise the principle of operation is the same as inthe standard mode.The third way to operate the chip is the pattern recog-nition or latch mode. In this mode 32 input channels areconnected to eight groups of fourfold latch-registers. Oncea leading edge of a signal is detected on a input channelthe fourfold input register is activated for the duration of apre-set time interval and subsequent hits on the other inputscan be registered as well. When the pre-set time has passed,the register is copied to the hit buffer and cleared for newrecording. While this transfer is realized a time-stamp withreduced resolution is taken and added to the informationfrom the register.In the fourth mode the chip can be used like any othernormal common-start TDC. After a start-signal on a dedi-cated start-input has been applied all subsequent time mea-surements are relative to this start-signal. In this mode thetime-stamps are immediately passed to the output bus andnot stored in the hit buffer. This mode does not make useof the trigger-matching possibilities of the TDC.Initialization of the F1-chip is performed via a 10 Mbpsserial connection. The interface for this link is integrated inthe TDC chip and no additional external control is needed.As an additional feature the F1 has eight eight-bit reg-isters and a dedicated interface to an eight channel digital-to-analog converter (AD8842) [5], which can be used forthreshold control of discriminator units placed on the front-end cards. The integration of the register and the interfacein the TDC avoids additional memory and controller unitson the front-end board.3 READOUT DRIVER BOARDS FORCOMPASSThe basic philosophy behind the COMPASS readout archi-tecture design was to unify as much hardware componentsas possible to save on spare parts and manpower duringpreparation and during the data-taking phase of the experi-ment. Having this concept in mind we decided to concen-trate the data as close as possible to the front-end into fewhigh-bandwidth data streams. A logic consequence was thedevelopment of a standardized data multiplexer board, theCATCH, for all the different components of the COMPASSdetector. The CATCH functions mainly as a derandomizerand must provide enough memory for intermediate storageof several events. To concentrate a large number of chan-nels we decided to build the CATCH as a 9U VME board.However, the VME bus will only be used for power dis-tribution, for transfer of set-up data during detector initial-ization and to spy on a sub-sample of events parasitically- but independent of the data acquisition system - duringdata taking.Data input to the CATCH can be performed in severalways. The data-interfaces to the CATCH are designed asmezzanine cards following the IEEE CMC standard [6].The advantage of mezzanine cards is that they allow easyand fast exchange without hardware modifications and thusgive the highest degree of flexibility. Currently we de-sign four different types of mezzanine cards: One cardcontains four 30 MByte/s HOTLink de-serializer receiver-chips [7] which will be used for front-end boards mountedon the detector; a second card contains F1-chips to assem-ble TDC boards; a third mezzanine card which containsseveral FPGA to implement fast 200 MHz dead-time-freescalers and a fourth card which will serve as an interface tothe silicon detector readout boards.The output of the CATCH module is connected throughthe P2 connector to a S-LINK multiplexer board mountedon the backplane of the VME crate. This multiplexer boardis used to optimize the transmission rate on the S-LINK tothe available S-LINK bandwidth, which is 100 MB/s/link.Figure 3 illustrates, as an example for the data flow on theCATCH, the use of the Cypress HOTLink receiver-chip asdata input source. In this example 24 bit data words aretransmitted in three words of one byte each.The data interfaces are scanned continuously for arriv-ing events. All data are reformatted to 32-bit words and, ifnecessary, additional hardware addresses are added. TheseTCSFibreROBparallel/serial (S-link mezzanine)Fibre 32 bit Data, 33 MHz max. (100 MByte/s)CATCH16 FE-boardsevent idserial/parallel (Cypress hotlink)8 bit wide FIFO (<128kbyte)decoder, event synchronizer8->24 bit, +8 bit adress id32 bit dataEvent mergingHeader / Event data FIFO16 x 300 MHz (30 MByte/s peak)Figure 3: Data flow in the CATCH module illustrated forwire chamber readout via HOTLink receivers.are transfered by the front-end only during the initializa-tion process for unambiguous identification. Next all datafrom a trigger are packed between a S-LINK header andS-LINK trailer. The S-LINK header and trailer contain aunique bit pattern for identification. Furthermore a S-LINKheader contains an event- and spill-number and describesthe data source and event type. For each individual eventthe information contained in the header is received by theCATCH from the Trigger Control System (TCS). The datafor one event are passed to the ROB when all front-endcards, which are connected to a CATCH, have transmit-ted either valid-data or an empty-data word for a particulartrigger-number.The CATCH module can also be used to erase data basedon second level decisions from the readout stream. To im-plement this feature in an experiment the trigger numbersof events, which are rejected by the higher trigger level,have to be distributed to the CATCH boards via the trig-ger control system. The latency of the second level trig-ger decision and the total data rate per CATCH determinesthe memory needed to store events before they are passedto the ROB. Currently the implementation of several datacompression methods on the level of the CATCH modulesare discussed as a possibility for further reduction of datarates.TCmezzanineSTrigger,clock,event idFibreCATCHCodingTCS Receiver40 MHz clockEvent idControl16 FE-boards40 MHzTrigger (coded)25ns trigger50ns time synctriggertime sync75ns user 1100ns user 2user 2user 1Figure 4: Trigger flow in the CATCH module.The handling of trigger signals from TCS on the CATCHboard is illustrated in Figure 4. The CATCH-module re-ceives trigger signals and a reference clock from the TCSvia optical data transmission. The TCS interface board con-tains an optical or copper cable receiver and a unit to de-code the time-division multiplexed signals transmitted bythe TCS. The TCS receiver board can be mounted to theP2 connector on the backplane of VME crates. Once theCATCH receives a trigger signal from the TCS it encodesthe signal as a pulse with the length of one clock cycle. Theencoded trigger signal is passed immediately to the front-end cards synchronous to the COMPASS reference clock(38.88 MHz). To check data for consistency a local eventnumber is generated and compared to the event numberstransfered with the data headers from the front-end.The physical network layer between front-end andCATCH is realized in standard S/STP CAT 6 [8] cable.This cable is widely used in Ethernet links between walloutlets and personal computers. The great demand for thiskind of cable makes it the cheapest solution to connect twopoints with four differential lines up to frequencies of 700MHz. In our application one differential line is used to dis-tribute the COMPASS 38.88 MHz reference clock to thefront-end. The second line is used to distribute up to fourdifferent user signals to the front-end. The signals are dis-tinguished by their length with respect to the COMPASSreference clock. One of the four possible signals is thetrigger-signal and another is a time synchronization reset atthe beginning of a spill. The remaining two can be definedaccording to user requirements. A third line is used for asserial link to down-load initialization data to the front-endelectronics at start-up. This serial line is operated at 10Mbps. The fourth line is used to transfer the serialized datafrom the HOTLink transmitter (front-end) to the HOTLinkreceiver (CATCH).4 ACKNOWLEDGEMENTThis work would be impossible without the significant ef-forts by the staffs of the collaborating institutions, in par-ticular those involved in front-end electronics development.The developments described in this report are supported bythe German Bundesministerium fu¨r Bildung, Wissenschaft,Forschung und Technologie.5 REFERENCES[1] E. van der Bij et al., S-LINK: A Prototype of the ATLASRead-out Link, Fourth Workshop on Electronics for LHC-Experiments, Rome, September 21-25 1998.[2] ANSI X3T9.3/91-005, High Performance Parallel InterfaceStandard.[3] Address: acam-messelectronic gmbh, Haid-und-Neu Str. 7,D-76131 Karlsruhe; EMAIL: support@acam.de.[4] IEEE P1596.3-1995, Draft Standard for Low-Voltage Dif-ferential Signals for Scalable Coherent Interface.[5] Analog Devices, Norwood, MA 02062-9106 Datasheet:AD8842, an 8-Bit Octal CMOS TrimDAC.[6] IEEE P1386, Standard for a Common Mezzanine Card Fam-ily: CMC.[7] Cypress Semiconductor, CY7B923/CY7B933 HOTLinkTransmitter/Receiver Preliminary data Sheet, CypressSemiconductor High Performance Data Book, August 1,1993.[8] ISO/IEC 11801:1995 Information technology – Generic Ca-bling for Customer Premises.

TDC Chip and Readout Driver Developments for COMPASS and LHC-Experiments

TDC Chip and Readout Driver Developments for COMPASS and LHC-Experiments

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