The aims of the CALICE test beam program are presented. The proposed
electronics readout system for the CALICE ECAL is described. It is a
purpose-built VME-based, unbuffered system.Comment: Conference proceedings for LCWS2002, Jeju Island, Korea, 26-30 August
  200

Dauncey, P. D.

English

arXiv

The aims of the CALICE test beam program are presented. The proposed electronics readout system for the CALICE ECAL is described. It is a purpose-built VME-based, unbuffered system.The aims of the CALICE test beam program are presented. The proposed electronics readout system for the CALICE ECAL is described. It is a purpose-built VME-based, unbuffered system

Dauncey, Paul D.

CERN Document Server

READOUT ELECTRONICS FOR THE CALICE ECALAND TILE HCALP. D. DAUNCEY∗ representing the CALICE-UK CollaborationPhysics Department, Imperial College London, UKAbstractThe aims of the CALICE test beam program are presented. The proposedelectronics readout system for the CALICE ECAL is described. It is a purpose-built VME-based, unbuered system.1 The CALICE CollaborationThe CALICE collaboration [1] is a group of 140 people from 24 institutes in Europe,US and Asia. The collaboration is planning a beam test program starting in 2004to study both electromagnetic (ECAL) and hadronic (HCAL) calorimeters for afuture linear collider (LC). The ECAL will be a silicon-tungsten sandwich samplingcalorimeter [2] and there are various options under investigation for the HCAL,namely using tile scintillators with analogue readout [3] or RPCs or GEMs withdigital readout [4] as the sensors. The main driver for these choices is the requirementof ne granularity for the \energy flow" algortihms used to obtain the jet resolutionsnecessary for LC physics [5].The beam test program will test the ECAL and all versions of the HCAL inan integrated data acquisition system so the data from both calorimeters can beanalysed together. It is planned to do a systematic study of the dependence of∗e-mail address: P.Dauncey@imperial.ac.uk12 International Workshop on Linear Collidersthe shower structure on particle energy, type and incident angle, as well as addinga \preshower" in front of the calorimeter to generate narrow cones of particles tosimulate jets. The total number of dierent congurations which will be tested is oforder 102, and to see the ne detail required, of order 106 events is estimated to beneeded for each conguration.2 ECAL electronicsThe CALICE beam test ECAL will consist of 30 layers of silicon and tungsten. Eachsilicon layer comprises nine wafers, each being a 6× 6 array of diode pads and eachof these is a readout channel. This gives 324 channels per layer, or 9720 channelsin total. These need to be read for every event, preferably without any threshold orother data suppression so as to allow pedestal and noise studies oine.The signals expected in the diodes range from the energy deposited by one mini-mum ionising particle (MIP) to around 1000 MIPs in the core of high energy electronshowers, a range of 10 bits. The intrinsic noise from the on-detector preamplier [6]is expected to be equivalent to around 0.1 MIP or less. It is of interest to measurethis noise level, so the dynamic range required is 14 bits in total. At the highestenergies of around 1000 MIPs, the resolution is degraded if the precision is below aMIP, so 10 bits of precision are required. The on-detector preamplier has a CR-RCshaper with a peaking time of 180ns. This denes the trigger latency needed toensure the waveform is sampled at this peak. A trigger jitter of 10ns is acceptable;this leads to a maximum shift below the peak of 0.1%, which is within the 10 bitsprecision requirement.The proposed system [7] is shown in gure 1. It consists of 15 identical read-out boards and a single trigger board. The readout boards handle the on-detectorpreamplier signals and all digitisation for two layers of the ECAL, or 648 channels.These signals are received on six cables per readout board. Each cable connectsto an electrically independent on-detector board which holds the preamplier andwhich handles three silicon wafers of 108 channels.The trigger board is a simple board to prevent further triggers until readout iscomplete and to distribute the trigger and the system clock across the backplaneto the readout boards. It contains very few components and will not be describedfurther below.LCWS(2002), Jeju, Korea 3x30 layersSi diode waferscablesTwisted−pairVFEchipsReadout boardx15 boardsTrigger board6U VME crateExternal triggerSROMSROM182pushbuttonconnectorsInputTriggerFPGAMaster11pushResetbuttonpathConfigurationdatapathdataeventFastDAC 21ADCx614624101611 6SlaveFPGA832VMEVME backplaneconnectorsTriggerand clockDifferentialdrivers andreceiversconvertersLevelFigure 1: Overview of the electronics system. The left gure shows the layout ofelectronics boards in the VME crate. The right gure shows the functional layoutof the readout board.An schematic diagram of the readout board is also shown in gure 1. The boardis controlled by a \master FPGA" which handles the VME interface and distributesthe clock and trigger from the backplane across the board. It interacts with the\slave FPGAs" by distributing conguration data (written to the board via VME)and collects the event data prior to VME readout.There is one slave FPGA for each cable from the on-detector electronics and sosix per readout board. Each operates independently of the others although theycontain identical rmware so, in standard operation, they would eectively be syn-chronised together. The slave FPGAs send the control and timing signals needed bythe on-detector electronics and receive six analogue signal lines. The 108 channelsare multiplexed onto these six lines, with 18 channels per line. The slave FPGAscontrol six 16-bit, 500kHz ADCs, one per signal line. The extra bits give robustnessagainst loss due to non-optimal range matching. The ADC speed results in a time todigitise all 18 channels of less than 50µs, or only 5% of the allowed 1ms event time.The trigger is also distributed to the on-detector electronics via the slave FPGAs,rounded to a 100 MHz clock, giving the required 10ns maximum jitter.To save any parallel development of similar electronics for the tile HCAL option,the on-detector electronics for this system is attempting to become similar enoughto the ECAL such that the same readout boards could be used for both. There will4 International Workshop on Linear Collidersbe around 1500 channels in the tile scintillator HCAL. The 16-bit ADC would bemore than ample for the range and precision required and would result in 3kBytesper event. The number of channels multiplexed per board for the HCAL is also notknown, so it is not clear how many extra readout boards would need to be fabricated.However, it is clear that a common solution would save signicant eort and is beingactively pursued by the groups involved.The maximum rate of data readout over VME is around 30MBytes/s. For adesired 1kHz rate, this implies the event size needs to be below 30kBytes. Therewill be no threshold suppression of the data on the readout board, so the ECAL datasize will be 19kBytes per event. Both options of the HCAL will be around 3kBytesand the size of any beam monitoring, particle idenitication and trigger data areuncertain, but likely to be around 1kByte. Hence, the total event size should bearound 25kBytes. This makes a 1kHz peak rate tight but not impossible. Thereadout board VME interface will be optimised for speed, using DMA transfers andasynchronous VME access. A fallback solution will be to split the system betweentwo or more crates, with two VME-PCI bus convertors.References[1] See http://polywww.in2p3.fr/tesla/calice.html.[2] J.-C. Brient, \Mechanical aspects of the R&D for the TESLA ECAL", theseproceedings; V. Vrba, \Silicon wafer production and processing for the TESLAW-Si ECAL", these proceedings.[3] V. Korbel, \Progress report on the TESLA tile HCAL option", these proceed-ings.[4] M. Martin, \A general high resolution digital hadron calorimeter using scintil-lator tiles", these proceedings; J. Yu, \Design of a digital HCAL with GEMs",these proceedings.[5] H. Videau, \How to test energy flow", these proceedings.[6] S. Manen, \Very front end electronics for a silicon tungsten calorimeter", theseproceedings.[7] See http://www.hep.ph.ic.ac.uk/calice/electronics/electronics.html.

Readout Electronics for the CALICE ECAL and Tile HCAL

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