BTeV is a $B$-physics experiment that expects to begin collecting data at the
C0 interaction region of the Fermilab Tevatron in the year 2006. Its primary
goal is to achieve unprecedented levels of sensitivity in the study of CP
violation, mixing, and rare decays in $b$ and $c$ quark systems. In order to
realize this, it will employ a state-of-the-art first-level vertex trigger
(Level 1) that will look at every beam crossing to identify detached secondary
vertices that provide evidence for heavy quark decays. This talk will briefly
describe the BTeV detector and trigger, focus on the software and hardware
aspects of the Level 1 vertex trigger, and describe work currently being done
in these areas

Gottschalk

Michael H.L.S Wang

English

arXiv

Crossref

BTeV Level 1 vertex trigger

BTeV is a B-physics experiment that expects to begin collecting data at the C0 interaction region of the Fermilab Tevatron in the year 2006. Its primary goal is to achieve unprecedented levels of sensitivity in the study of CP violation, mixing, and rare decays in b and c quark systems. In order to realize this, it will employ a state-of-the-art first-level vertex trigger (Level 1) that will look at every beam crossing to identify detached secondary vertices that provide evidence for heavy quark decays. This talk will briefly describe the BTeV detector and trigger, focus on the software and hardware aspects of the Level 1 vertex trigger, and describe work currently being done in these areas

Wang, Michael H.L.S.

UNT Digital Library

Fermilab FERMILAB-Conf-01/336-E  BTeV  Nov. 2001BTeV Level 1 Vertex TriggerMichael H.L.S. WangFor the BTeV CollaborationFermi National Accelerator Laboratory, Batavia, IL 60510, USAAbstractBTeV is a B-physics experiment that expects to begin collecting data at the C0interaction region of the Fermilab Tevatron in the year 2006. Its primary goal isto achieve unprecedented levels of sensitivity in the study of CP violation, mixing,and rare decays in b and c quark systems. In order to realize this, it will employa state-of-the-art rst-level vertex trigger (Level 1) that will look at every beamcrossing to identify detached secondary vertices that provide evidence for heavyquark decays. This talk will briey describe the BTeV detector and trigger, focuson the software and hardware aspects of the Level 1 vertex trigger, and describework currently being done in these areas.1 BTeV DetectorThe BTeV detector is a collider detector with two back-to-back forward spec-trometers (1:5 < jj < 4:5) having sub-detectors in each arm for chargedparticle tracking, EM calorimetry, RICH particle ID and muon detection [1].At the core of the detector is a 30 station Si-pixel inner tracker spanning 120cm centered at the IR (z = 30 cm) and immersed in a 1.6 Tesla dipole eld.There are over 20  106 active rectangular pixels measuring 50  400 m2.Each pixel station has two planes, one with narrow pixel dimension orientedin the x-direction and the other with narrow dimension in the y-direction.2 BTeV TriggerBTeV will operate at a luminosity of 2 1032 cm 2 s 1 corresponding to h2iinteractions per beam crossing at a crossing rate of 7.6 MHz. Average eventsizes will be 200 KB after zero-suppression of data is performed on-the-yPreprint submitted to Elsevier Science 1 November 2001BTeV detectorL1 muonL1 vertexGlobalLevel-1Level-1Level 2/3 Crossing SwitchData LoggingFront-end electronicsLevel-1 BuffersLevel-2/3 BuffersInformation TransferControl HardwareITCHLevel-2/3 ProcessorFarm#1#2#m-1#mRDYCrossing #NReq. data forcrossing #NLevel-3 acceptGL1 acceptPIXµ µ> 3 x 10 channels7Fig. 1. BTeV Three-Level Trigger Architectureby front-end detector electronics. Since every beam crossing will be processed,this translates to an extremely high data rate of 1.5 TB/sec!To handle this high rate, BTeV will employ a three-level hierarchical triggerarchitecture [2] (see Fig. 1). Sparsied data from all detector components willbe sent via optical links to Level 1 (L1) buers. Data from the pixel and muondetectors will also be sent to the L1 trigger processor. Trigger decisions fromthe L1 muon and vertex trigger will be passed on to the Global Level 1 (GL1)trigger manager whose decisions will be stored as a list of accepted crossingnumbers by the Information Transfer Control Hardware (ITCH). L1 will reject99% of all incoming events reducing the data rate by a factor of 100 to 15GB/sec.Levels 2 & 3 (L2/3) will be implemented with a cluster of commodity CPUnodes. A request from an idle L2 node will be sent to the ITCH which willrespond by assigning an accepted crossing number to that node. This node willthen request a subset of the data (pixels+forward tracking) for that crossingfrom the L1 buer managers. A switch will combine pixel data with forwardtracking data for the same crossing and route them to the buer of an L2 nodeallowing a more rened analysis that will further reduce the data rate by afactor of 10.If that passes the L2 selection criteria, the same processing node will then2enter the L3 phase and request data from the rest of the sub-detectors betransferred from the L1 to the L3 buers (L2/3 buers will simply be theRAM attached to the processing node). Using complete information from thedetector, L3 will reduce the crossing rate by an additional factor of 2. SinceL3 will also be able to further compress the data in the accepted crossings bya factor of 4, the expected data rate out of L3 is 200 MB/sec.3 Level 1 Vertex Trigger AlgorithmThe rst phase of the L1 vertex trigger algorithm is the track nding phase[3] which starts by nding the beginning and ending segments of tracks in twoseparate regions of the pixel planes, an inner region close to the beam axisand an outer region close to the edge of the pixel planes. The search for thebeginning and ending segments of tracks is restricted to these inner and outerregions respectively. Segments are found using hit clusters from three adjacentpixel stations in the dened regions. Inner segments are required to point backto the beam axis while outer segments are required to project outside pixelplane boundaries. Once these segments are found, they are then matched toform complete tracks in the segment matching stage.After complete tracks are found, the vertexing phase [4,5] determines the mo-mentum of each track and calculates its transverse distance from the beamaxis. Primary vertices are found by looping through all tracks with transversemomentum pT  1:2 GeV/c that appear to originate close to the beamline.Remaining tracks are then tested for their detachment from the primary ver-tices found. A L1 vertex trigger is generated if there are at least 2 tracks inthe same arm of the BTeV detector satisfying the following criteria: p2T 0:25(GeV/c)2, b  6, and b  2mm where b is the impact parameter.Our studies indicate that the L1 vertex trigger is able to reject 99% of allminimum-bias events while accepting 60-70% of the B-events that wouldsurvive our oine analysis cuts.4 Level 1 Vertex Trigger HardwareA block diagram of the L1 vertex trigger is shown in Fig. 2. Data from all 30stations of the pixel detector are sent to FPGA based pixel processors thatgroup individual pixel hits into clusters. Hit clusters from three neighboringpixel stations are routed to FPGA based hardware that nd beginning andending segments of tracks in the track nding phase.330 Pixel StationsPixel ProcessorsFPGA Segment Finders~2,500-node DSP track/vertex farmSwitch (sort by crossing number)MERGETo Global Level-1 (GL1)Fig. 2. BTeV Level-1 vertex trigger.Segments found in this stage are sorted by a switch according to crossingnumber and routed to a DSP in the track/vertex farm. This DSP performsthe segment matching step of the track nding phase and the entire vertexnding phase. Based on initial studies done for the BTeV proposal [1], weestimate the average processing time for the combined segment matching plusvertex nding phase to take 330 s on a single 167 MHz TI TMS320C6711oating point DSP. Since the time between beam crossings is 132ns, this willrequire a total of 2,500 DSP in the track/vertex farm in order to examineevery beam crossing.5 Work in ProgressSince hand-optimized assembly code can be diÆcult to maintain and debug,we are working on an optimized C version of the L1 segment matching andvertexing code. A version is currently running on a C6711 DSK board in whichwe have replaced costly function calls with intrinsics that map directly tobuilt-in DSP instructions and completely rewritten major sections of the code.Preliminary results indicate that this optimized C version is only a factor of4-5 slower than the hand-optimized assembly version used for initial timingestimates. While we expect substantial gains in DSP chip performance in thenext few years, we will continue to explore ways to improve code performance,resorting to hand-optimized assembly programming only when necessary.4We are developing a prototype board for the segment matching and vertex-ing portion of the L1 trigger with four DSP's on mezzanine cards. OnboardFPGA input and output buers will have an LVDS interface to a host com-puter through which simulated data can be sent. Buer managers in the FPGAwill channel data to and from each DSP via DMA transfers. Trigger resultsfrom each processor will be sent through an FPGA interface to an on-board-controller that will format the results and forward them to GL1 throughArcNet. A host computer serving as a pixel trigger supervisor monitor will beconnected to a second on-board -controller through ArcNet, allowing com-mands to be sent to the board, initialization of the DSP's, and providinghardware monitoring and fault detection. JTAG ports will also be availablefor real-time debugging and initial start-up of the prototype.We are also implementing the L1 segment nding algorithm in FPGA's anddoing simulations and queuing studies of the algorithm with MATLAB.As a nal note BTeV will greatly benet from a newly approved NSF fundedproject called RTES (Real Time Embedded Systems) [6] which will develop asemi-autonomous, self-monitoring, fault-tolerant and adaptive framework foraddressing issues facing complex computing architectures like that of BTeV.6 ConclusionWe have designed a Level 1 vertex trigger that will address the demandingrequirements of BTeV. We are currently working on optimizing a high-levelversion of the vertex trigger algorithm and developing a prototype board forinvestigating various aspects of the L1 vertex trigger hardware.References[1] A. Kulyavtsev et al., BTeV proposal, Fermilab, May 2000.[2] P. Lebrun, The BTeV triggers and data acqusition systems, talk presented at thesession on New Detector Technologies, at the meeting of the Division of Particlesand Fields of The American Physical Society, Columbus, OH, August 9-12 2000.[3] E.E. Gottschalk, BTeV detached vertex trigger, Nucl. Instrum. Meth. A 473(2001) 167.[4] R. Isik, Real-time pattern-recognition for HEP, University of Pennsylvania,preprint UPR-233E, 1996.[5] R. Isik, W. Selove, K. Sterner, Monte Carlo results for a secondary-vertex triggerwith on-line tracking, University of Pennsylvania, preprint UPR-234E, 1996.5[6] E.E. Gottschalk, The BTeV DAQ and trigger system- some throughput, usabilityand fault tolerance aspects, Proc. CHEP 2001, Beijing, Sept. 3-7 2001, p. 628.6

BTeV level 1 vertex trigger

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BTeV Level 1 Vertex Trigger

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