Hybridization of pixel detector systems has to satisfy tight requirements:
high yield, long term reliability, mechanical stability, thermal compliance and
robustness have to go together with low passive mass added to the system,
radiation hardness, flexibility in the technology end eventually low cost. The
current technologies for the interconnection of the front-end chips and the
sensor are reviewed and compared, together with the solutions for the interface
to the far-end electronics.Comment: 7 pages, no figure, presented at PIXEL2000, International Workshop on
  semiconductor pixel detectors for particles and X rays, 5-8 June 2000,
  Genova, Italy. Proceedings to be published in Nuclear Instruments and Methods
  in Physics Researc

Becks

Bonvicini

Chochula

Heijne

Heuser

Humpston

Massimo Caccia

Miller

Pfeifer

Salonen

Soper

Yung

English

arXiv

Hybridization of pixel detector systems has to satisfy tight requirements: high yield, long term reliability, mechanical stability, thermal compliance and robustness have to go together with low passive mass added to the system, radiation hardness, flexibility in the technology end eventually low cost. The current technologies for the interconnection of the front-end chips and the sensor are reviewed and compared, together with the solutions for the interface to the far-end electronics.Hybridization of pixel detector systems has to satisfy tight requirements: high yield, long term reliability, mechanical stability, thermal compliance and robustness have to go together with low passive mass added to the system, radiation hardness, flexibility in the technology end eventually low cost. The current technologies for the interconnection of the front-end chips and the sensor are reviewed and compared, together with the solutions for the interface to the far-end electronics

Caccia, Massimo

CERN Document Server

arXiv:hep-ex/0101011v1  10 Jan 2001The challenge of hybridizationMassimo Caccia aaUniversita’ dell’Insubria, Via Valleggio 11, Como, ItalyAbstractHybridization of pixel detector systems has to satisfy tight requirements: high yield,long term reliability, mechanical stability, thermal compliance and robustness haveto go together with low passive mass added to the system, radiation hardness,flexibility in the technology end eventually low cost. The current technologies for theinterconnection of the front-end chips and the sensor are reviewed and compared,together with the solutions for the interface to the far-end electronics.Key words: Hybridization; bump bonding; Silicon detector; pixel1 IntroductionMoving from a detector prototype toa full scale system, integrated in alarge experimental facility, requiresa full production chain optimizationwhere hybridization plays a crucialrole. As a case study, the pixel de-tector for the DELPHI experiment atLEP may be considered (1). As anupgrade of the existing Silicon stripvertex detector, pixel sensor endcapswere installed, covering the low polarangle region (10− 25o) and improv-ing the hermeticity (2). The detectorwas installed in 1996 and it has beenrunning for ≈ 8 months a year since1997 without hardware interventionsor dismantling, achieving the designperformances. The DELPHI pixel de-tector represents a succesful pioneer-ing project; nevertheless, it appearsas being simple compared to the nextgeneration of detectors planned forthe future experiments at the LargeHadron Collider at CERN and theTevatron at Fermilab (3; 4; 5; 6):• the DELPHI detector is made upof 152 modules, for ≈ 1.2× 106pixels. In the future detectors, thenumber of modules increases by afactor 20 and the number of pixelsby two orders of magnitude.• DELPHI pixels were meant fortracking in a low redundancy re-gion rather than vertexing. Thisis the reason for the pixel cell sizeto be 330× 330µm2 in DELPHI,scaled down to a 50µm minimalpitch and area ≈ 10−4cm2 in thefuture applications where vertex-ing is a must. For the same region,the material budget at LHC andTevatron is quite tight. At thePreprint submitted to Elsevier Preprint 11 February 2014moment, the sensor and front endchip assembly, the substrate forthe power bus and control linesand the mechanical support con-tribute to the passive material (inradiation length) according to theratio 1 : 0.4 : 1.5. If the mechanicsis still dominating, the bus sub-strate is far from being negligible.• LEP is a radiation soft environ-ment and levels below 1 Krad/yearare measured. At LHC, the dose isexpected to increase by three or-ders of magnitude, for an equiva-lent flux of 1 Mev energy neutrons≈ 1014cm−2 per year at the vertexdetector radii. As a consequence,all of the hybridization and assem-bly technologies have to be quali-fied as radiation hard. Moreover,while the DELPHI pixels are op-erated at room temperature, thefuture detectors will run at around−10 oC and effects related to mis-matches among the coefficients ofthermal expansion of the assemblyare critical.• the DELPHI pixels are clockedat 5MHz while the future experi-ments requires a 40MHz clock, sothat the properties of the striplinetransmission lines have to be qual-ified.Irrespective of the rather soft bound-ary conditions outlined above, thefinal production yield of the DEL-PHI pixels was at the 40% level (7).In particular, bump bonding andassembly were rather critical, withefficiencies at the 80% and 55% re-spectively. The future pixel detec-tors have a 70% production yieldbenchmark and much more criticalconstraints; achieving it without de-grading the expected performancesand fitting the time scale is the realchallenge of hybridization.In the following, bump bonding is-sues and techniques for the signal andpower line routings are reviewed, out-lining the main advantages and dis-advantages.2 Front-end chip and sensor in-terconnectionDue to the contact density(5000− 10000cm−2), minimum pitch(50µm), and the required singlebump failure rate (< 10−4) the onlyinterconnection technique is bumpbonding of flipped chips. Stencilprinting of conductive glue has beenproven to work at larger pitch (8);anisotropic conductive film is alsoused by industry at larger pitches,especially for LCD packaging; studbonding may be considered for pro-totyping as single dies can be bondedbut it is not an option by now for abatch production.The choice of the metal bump,whether it is going to be Indium or asolder paste, determines the processcharacteristics in terms of the un-der bump metallization (UBM), thebonding mechanism and parameters,the mechanical properties and thebump aspect ratio.22.1 Solder bumpsSolder bumps have been introducedabout 30 years ago by IBM to over-come the limits of wire bonding. Thesteps of the original IBM C4 process(Controlled Collapse Chip Connec-tion (9)) may be summarized as fol-lows:• after the wafer is cleaned, the un-der bump metal layers are grownon the final pad by evaporationthrough a molybdenum mask,with ultimate via size of 50µm.The UBM is meant to provide:· an adhesion layer (”activemetal”,usually Cr or Ti:W) on top ofthe final metal pad· a barrier layer (phased Cr-Cu) toprevent the solder dissolving theactive metal· a solder wettable layer (Cu or Ni)· an oxide prevention layer (Au)• a lead rich solder (either 97Pb/Snor 95Pb/Sn) is evaporated throughthe mask, for bumps diameter andheight in the 100− 125µm range• the wafer is heated up to the phasetransition temperature, that de-pends on the solder compositionand may achieve a maximum of≈ 350oC (”reflow”). Because ofsurface tension, the bump will un-dergo a predictable collapse to anequilibrium shape correspondingto a truncated sphere (10). Re-flow may occurr in presence of asuitable flux or in an organic com-pound bath.The original IBMprescription presentsthree major limitations (11; 12; 13):because of the mismatch betweenthe Silicon and Molybdenum coeffi-cients of thermal expansion the pro-cess cannot be effectively scaled uppast 5 inch wafers; the finite maskthickness and the mask alignmentprocedure limits the typical pitch to250µm; eutectic Pb/Sn solder can-not be evaporated due to the lowvapour pressure of the Sn. The useof eutectic solder bumps (37Pb/Sn,with a reflow temperature of 230oC))is pursued by industry as it providesthe option of mounting the IC ontothe circuit board using the sametechniques employed for the surfacemountable components. These lim-itations are currently overcome byelectroplating the UBM and the sol-der in a pattern defined by photore-sist masks (13; 14). Critical param-eters in this case are solder heightand alloy uniformity, linked to thecontrol of the plating current andsolution flow; solder voiding has alsobeen reported (12; 13), connected tohydrogen entrapment in the platingsolution. Industrial standards corre-spond to 150µm pitch for 70− 80µmfootprint.Surface tension effects during thereflow are essential during the flip-chip attachment, as they induce self-alignment and planarization of thechip with respect to the substrate(15). As a consequence, effectivebonding is achieved for overlaps be-tween the bond and the wettablesubstrate pad exceeding 25% of thepad area.The main issues making the solderbump techniques appealing for theinterconnection of sensors and front-end chips are: bump uniformity and3self-alignment properties, resultingin a low single bump failure rate;the optimal height/pitch ratio, e.g.15− 20µm height for a 50µm pitch(16; 17), limiting the parasitic capac-itance also in a single sided process;the excellent electrical properties(contact resistance at the mΩ level(17)). On the other hand, there arecritical issues that should not be un-derestimated as they could affect theinterconnection reliability: the UBMis quite complex and a not perfectcontrol of the metallurgy can resultin a poor adhesion; the process re-quires relatively high temperaturesteps, that might not be toleratedby radiation hard processes; the re-flow chemistry should guarantee wirebondability of the I/O pads. Ther-mal fatigue and high stress inducedby mismatches in the coefficient ofthermal expansions of the assem-bly are also of concern (18; 19); themechanical properties (in terms ofultimate tensile and shear stress)depends on the bump dimensions,on the UBM characteristics and thesubstrate material but in general fa-tigue life is increased by the use ofa filler between the substrate andthe chip (12), possibly not toleratedin assemblying detectors. In currenthigh energy physics applications, upto 16 chips are connected to samesubstrate; replacing a faulty chip(”reworking”) could considerably im-prove the yield. For instance, in theDELPHI pixel detector the moduleproduction yield after bump bondingof 16 known good chips was 80% anda good part of the faults were on asingle chip. Reworking chips as closeas 50µm is not trivial in term of therequired temperature and stress andmostly because residual solder has tobe cleaned before the new placementoccurs.Nevertheless, excellent results wereobtained on small volume detectorassemblies for the WA97 (20) andDELPHI experiments (2) and onprototypes for the ATLAS experi-ment (21), with single bump failurerate in the 10−4 − 10−5 range andpitch down to 50µm. The results ob-tained so far proves the technologyis mature and solutions to specificproblems certainly benefits of theenourmous knowledge gained to de-fine an industrial standard.2.2 Indium bumpsIndium bumping technology hasbeen developed for Infrared Sensorassemblies as In retains its mechani-cal properties also at liquid Nitrogentemperature where the sensors areoperated. In bumps are in generalgrown by evaporation through a pat-terned photoresist, after a properUBM. The UBM may be simple andlimited to a single Cr adhesion layerand bump pitches in the 20− 30µmare standard (22). Chemical etch-ing of the photoresist and evapora-tion are critical parameters in theprocess, as a bad control may re-sult in Indium attachment to thevia walls, making the lift-off not ef-fective (11; 22). As a result of it,In bumps have a small height/pitchratio (e.g. 7µm/50µm) and bump-ing on both sides of the dies beingassembled may be necessary (23).Indium belongs to the third group4of the periodic table and it featuresa remarkable tendency to form anoxide crust (its electrode potential is+0.38 V, to be compared to +1.66 Vfor Al). As a result of it, bump reflowis extremely difficult even if possibleaccording to proprietary processes(see for instance (24)). Solid statediffusion bonding occurs at mod-erate pressure (10−2N/bump) andtemperature (20− 100oC) (22; 23),but it requires excellent planarity (atthe 0.1mrad level) and bump unifor-mity. The latter is the most criticalpoint of the In bumping technology,together with a possible electronicsnoise increase due to the ”small”bumps. The remarkable points maybe summarized in the simple UBM,the low bonding temperature and thefact that industry standards matchthe requirements for detector as-sembly. Reworking appears simpleras the In left over on the substratemay be used for the fresh substrateattachment. Indium plastic proper-ties should help in system assemblybut this has to be traded off witha lower shear and tensile strengthwith respect to solder bumps. Theultimate tensile strength for SnPbbumps has been measured to be inthe 25− 50MPa range (18), to becompared to 1.9MPa for In at roomtemperature (25); the ultimate shearstress for solder bumps is in the 25-40MPa range, while for In is 6.1 MPa.Excellent results on detector assem-blies have been obtained on proto-types for the ATLAS and CMS pixeldetectors and have been reported atthis conference (23; 24; 26); the sin-gle bump failure has been measuredto be at 10−5 level and the system re-liability is under investigation.2.3 ConclusionFlip chip technologies based on bothsolder and Indium bumps have beenproven to be a solution for detectorassembly. The statistical single bumpfailure rate is well within the specifi-cations. The choice between either ofthe two technologies will possibly bedefined by the long term reliability,the thermal compliancy of the assem-blies and by the quality of the processcontrol, i.e. by its repeatibility.3 Power lines and signal busAfter the front-end chips are bumpbonded, the assembly of a module iscompleted routing the power and dig-ital lines, housing the controller chipand eventually temperature sensorsand the opto-package for the inter-face to the far-end electronics. Thismay be accomplished by two differ-ent approaches:• the ”flex” hybrid technology,where routing is defined in a mul-tilayer polyimide film glued onthe substrate. The passive compo-nents are connected with standardsurface mount technology andwire bonds interconnect the tracesto the I/O pads of the front-endchips. The controller chip may beconnected either by wire bonds orflip chip. This approach was usedin DELPHI (1) and it is consideredthe baseline option for the pixel5detectors at the LHC experimentsand BTeV, reporting the latestdevelopments at this conference(4; 27; 28)• the Multi Chip Module with De-posited Dielectric (MCM-D) tech-nology, a robust and monolithicapproach based on thin film tech-nology (17). In MCM-D, routing isagain defined in a multilayer filmbut grown on the substrate, wherethe dielectric is deposited by spincoating and the traces are electro-plated. Passive components maybe integrated in thin film tech-nology and the chip I/O pads areinterconnected by bump bonding.This approach is being developedfor the ATLAS pixel detector;the basic principles and the lat-est developments have also beenreported at this conference (29).The two solutions are similar as faras the passive material added tothe system (≈ 0.1% X0 (30)) andopposite in any other respect. Flexhybrids are a mature industrial tech-nology and the requirements for thegeneric detector assembly fit thestandards. Wire bonding reliabilityis a concern but it is not expectedto be critical. The main issue is thevery large mismatch between thecoefficients of thermal expansion offlex (≈ 45× 10−6 oC−1) and Silicon(2.5× 10−6 oC−1) that can induce asevere stress on the bumps movingfrom the assembly to the operat-ing temperatures, i.e. from 20oC to≈ −10oC (26). The MCM-D technol-ogy offers the advantages and disad-vantages of a monolithic approach.On one hand, no wire bonds are fore-seen and the assembly scheme min-imizes the stress on the bumps, asthe multilayer is to be grown on thejunction side of the sensor. On theother hand, the requirements on thesingle bump failure rates are tighter,as the front-end I/O pad are alsobump bonded; moreover, each sen-sor cell is connected to the matingelectronics cell by a staircase of feedthrough connections also requiringa high quality assurance. Last butnot least, the MCM-D is necessar-ily tested after being grown on thesensor substrate so the possibilityto rework the substrate in case offailure is a must in terms of yieldoptimization. The current resultsdemonstrate the integrated solutionis certainly appealing but the pro-cess optimization is still under way,both in industrial applications andin detector assembly.4 ConclusionsThe next generation of pixel detec-tor trackers represents a real chal-lenge as every system characteristicsis at the edge of the current technol-ogy. Moreover, the total area is suchthat the proposed solutions have alsoto guarantee a high production yield.Hybridization is not less demanding:suitable technologies exist and qual-ity assessment is on the way, with afull qualification by the productionstarting soon.6References[1] K.H. Becks et al., Nucl. In-strum. Methods Phys. Res. A418 (1998) 15.[2] P. Chochula et al., Nucl. In-strum. Methods Phys. Res. A412 (1998) 304.[3] V. Vrba, these proceedings[4] D. Kotlinski, these proceedings[5] F. Meddi, these proceedings[6] C. Newsom, these proceedings[7] J. Heuser ,Nucl. Phys. B, Proc.Suppl. 78 (1999) 269.[8] V. Bonvicini et al. ,Nucl. Phys.B, Proc. Suppl. 44 (1995) 409.[9] L.F. Miller , IBM J. of Res. andDev. 13 (1969) 239.[10] M.J. Pfeifer , IEEE Trans. onComp., Pack.,Manufact. Tech-nol. B 20 (1997) 452.[11] E. Jan Vardaman et al.,Worldwide developments inflip chip interconnect (Tech-Search International, Inc.,Austin, Texas, U.S.A., 1994)[12] D.S. Patterson et al, Proc. IN-TERPACK ’97 EEP-Vol.19-1 (1997) 337. Also available athttp://www.flipchip.com/flipsec4/tec.htm[13] E.K. Yung et al. , IEEE Trans.on Comp., Hybrids, Manuf.Technol. 14 (1991) 549.[14] J. Salonen et al. , Phys. ScriptaT54 (1994) 23[15] J.F. Kuhmann et al. , IEEEPhoton. Techn. Lett. 8 (1996)1665. and references therein.[16] G. Humpston et al. , Nucl. In-str. and. Meth. in Phys. Res. A395 (1997) 375.[17] M. Topper et al. , Proc.Int. Conf. on High DensityPackaging and Multichipmodules Denver, U.S.A.,apr. 6-9, 1999, also avail-able at http://www.uni-wuppertal.de/FB8/groups/Teilchenphysik/det ver.english.html[18] A.Soper et al. , Microelectron.Reliab. 37 (1997) 1783.[19] J.H. Lau , IEEE Trans. onComp., Pack., Manufact. Tech-nol. B 19 (1996) 728.[20] E.H.M. Heijne et al. , IEEETrans.Nucl.Sci. 42 (1995) 413.[21] J. Wolf, these proceedings[22] A.M. Fiorello, these proceed-ings[23] C. Gemme, these proceedings[24] R. Horisberger, these proceed-ings[25] data by the Indium Corpora-tion of America,http://www.indium.com[26] P. Netchaeva, these proceed-ings[27] P. Skubic, these proceedings[28] S. Zimmermann, these proceed-ings[29] C. Grah, these proceedings[30] The ATLAS collaboration,Pixel Detector-Technical de-sign report , CERN/LHC98-13, pag.2907

The challenge of hybridization

CACCIA, MASSIMO

Archivio istituzionale della ricerca - Università dell'Insubria

Crossref

Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment

The challenge of hybridization

Abstract

Similar works

Full text

Available Versions

CERN Document Server

Archivio istituzionale della ricerca - Università dell'Insubria

Crossref