Limitations in traditional scaling methods require novel devices to increase computational density without scaling down device size. Ferroelectric materials’ negative capacitance property reduces the subthreshold slope beyond the previous theoretical ideal of 60 mV/decade and improves computational density without reducing transistor size. The research herein characterizes fields in isolated ferroelectric material, ferroelectric-oxide interfaces, and ferroelectric material integrated in the gate-stack of a ferroelectric nanowire-FET (FeNW) to achieve sub 60 mV/decade subthreshold slope. The research attains sub 60 mV/decade subthreshold slope across multiple FeNW configurations, and subsequently provides a ferroelectric-to-oxide capacitance, ratio-based design method to approaching sub-60 mV/decade subthreshold slope and narrowing the device design space. The research concludes by disclosing design tradeoffs when attaining sub 60 mV/decade subthreshold slope, to provide an engineer or physicist insight on the applications and limitations of the present state of ferroelectric nanowires and ferroelectric FETs
