Novel Cell Architecture for High Performance of 512-Mb DRAM with 0.12-??m Design Rule

Abstract

In this research, the data retention time was investigated for a high-speed the 0.12-um, low power 512-Mb DRAM (Dynamic Random Access Memory) with 0.12 ??m design rule. As the technology generation of DRAM has been developed into sub-quarter micron region, the control of the junction leakage current at the storage node has become much more important due to the increased channel doping concentration. In order to obtain high-performance DRAM with the 0.12-??m design rule, we propose a novel trench isolation (shallow trench isolation) using self-aligned local field implantation to improve the data retention-time characteristics and to minimize the narrow-width effect in the cell transistor. This scheme reduces both the cell junction leakage current and the capacitance by relaxing the abrupt junction profile at the source and the drain regions. The relaxed junction profile can reduce the electric field strength of junction and, thus, improve the data retention-time characteristic of the DRAM. We also tried to cure the surface defect by using a gate dual spacer and downstream Si-treatment. A high capacitance is realized by the dual molded oxide capacitor process. This novel storage node structure gives the capacitor much better mechanical stability. With the novel cell architecture, dramatic increases in the data retention time and the device yield were obtained for a 512-Mb DRAM. The proposed cell architecture can be extended fairly well to future high-density DRAM in 0.10 ??m technology and beyond