Department of Computer Science and EngineeringTransaction Processing Systems are widely used because they make the user be able to manage
their data more efficiently. However, they suffer performance bottleneck due to the redundant
I/O for guaranteeing data consistency. In addition to the redundant I/O, slow storage device
makes the performance more degraded. Leveraging non-volatile memory is one of the promising
solutions the performance bottleneck in Transaction Processing Systems. However, since the
I/O granularity of legacy storage devices and non-volatile memory is not equal, traditional
Transaction Processing System cannot fully exploit the performance of persistent memory.
The goal of this dissertation is to fully exploit non-volatile memory for improving the performance
of Transaction Processing Systems.
Write amplification between Transaction Processing System is pointed out as a performance
bottleneck. As first approach, we redesigned Transaction Processing Systems to minimize the
redundant I/O between the Transaction Processing Systems. We present LS-MVBT that integrates
recovery information into the main database file to remove temporary files for recovery.
The LS-MVBT also employs five optimizations to reduce the write traffics in single fsync() calls.
We also exploit the persistent memory to reduce the performance bottleneck from slow storage
devices. However, since the traditional recovery method is for slow storage devices, we develop
byte-addressable differential logging, user-level heap manager, and transaction-aware persistence
to fully exploit the persistent memory. To minimize the redundant I/O for guarantee data consistency,
we present the failure-atomic slotted paging with persistent buffer cache.
Redesigning indexing structure is the second approach to exploit the non-volatile memory
fully. Since the B+-tree is originally designed for block granularity, It generates excessive I/O
traffics in persistent memory. To mitigate this traffic, we develop cache line friendly B+-tree
which aligns its node size to cache line size. It can minimize the write traffic. Moreover, with
hardware transactional memory, it can update its single node atomically without any additional
redundant I/O for guaranteeing data consistency. It can also adapt Failure-Atomic Shift and
Failure-Atomic In-place Rebalancing to eliminate unnecessary I/O.
Furthermore, We improved the persistent memory manager that exploit traditional memory
heap structure with free-list instead of segregated lists for small memory allocations to minimize
the memory allocation overhead.
Our performance evaluation shows that our improved version that consider I/O granularity
of non-volatile memory can efficiently reduce the redundant I/O traffic and improve the
performance by large of a margin.ope
