This paper discusses problems encountered with control networks in highly restructurable digital systems. In particular the treatment of implementation errors is covered with emphasis on concurrent processing. The implementation of concurrent processing networks may result in errors which will be quite complex to detect and systematic methods are warranted. Four meta control elements are employed in obtaining convenient concurrent structures. We analyze several error detecting schemes and conclude that the arc-node method with node partitioning appears to be the most realistic approach at this time

Ellis, Robert A.

Keller, Robert M.

Stucki, Mishell J.

Wann, Donald F.

English

Keck Graduate Institute

Claremont Colleges
Scholarship @ Claremont
All HMC Faculty Publications and Research HMC Faculty Scholarship
9-1-1967
Problems Encountered With Control Networks in
Highly-Restructurable Digital Systems
Donald F. Wann
Robert A. Ellis
Mishell J. Stucki
Robert M. Keller
Harvey Mudd College
This Article is brought to you for free and open access by the HMC Faculty Scholarship at Scholarship @ Claremont. It has been accepted for inclusion
in All HMC Faculty Publications and Research by an authorized administrator of Scholarship @ Claremont. For more information, please contact
scholarship@cuc.claremont.edu.
Recommended Citation
Wann, D.F., R.A. Ellis, M.J. Stucki, and R.M. Keller. "Problems encountered with control networks in highly-restructurable digital
systems." Digest of the First Annual IEEE Computer Conference (September 1967): 29-32.
D.F. Wann
PROBLEMS ENCOUNTERED WITH CONTROL NETWORKS
IN HIGHLY RESTRUCTURABLE DIGITAL SYSTEMS
R.A. Ell is M.J. Stucki
Washington University
St. Louis, Missouri
R.M. Keller
ABSTRACT. This paper discusses problems encountered with control networks in highly restructurable
digital systems. In particular the treatment of implementation errors is covered with emphasis on con-
current processing. The implementation of concurrent processing networks may result in errors which will
be quite complex to detect and systematic methods are warranted. Four meta control elements are employed
in obtaining convenient concurrent structures. We analyze several error detecting schemes and conclude
that the arc-node method with node partitioning appears to be the most realistic approach at this time.
Introduction
In this paper we discuss aspects of concurrent
control structures encountered in the context of
the Macromodular Project being carried out at Wash-
ington University. (1) (2) Although many of the
ideas to be presented apply specifically to macro-
modular systems, we feel that these systems are the
first of a new class of highly-restructurable sys-
tems, (3)(4) and that the considerations to be dis-
cussed are characteristics of this class.
Macromodules are digital building blocks that
are rather unique in that data processing struc-
tures constructed from them are isomorphic to a
directed graph and can, therefore, be designed and
analyzed from a graph-theoretic viewpoint. The
nodes of the graph correspond to the macromodules
themselves and the arcs of the graph correspond to
the control cables that interconnect the modules.
All electrical and mechanical considerations have
been eliminated by careful design of the units,
and the design of data processing structures is
therefore an exercise in logic only.
The macromodular concept makes possible data
processing avenues not possible in fixed structured
systems. Specifically, the ease with which macro-
modular structures may be re-configured and aug-
mented makes it possible for a system user to alter
a system's configuration so as to be more efficient
for his particular problem area. There are many
ways in which the efficiency of a system may be
affected: machine instructions may be changed to
better fit the problem area, machine instructions
may be re-designed in a highly parallel or con-
current fashion to minimize the operating time of
the system, etc .• As is to be expected, however,
opportunities such as these are not without accom-
panying pitfalls. It has been discovered that in
the process of formatting a system alteration and
implementing it into the system it is extremely
easy to make what we shall call "implementation
errors" as contrasted to algorithm errors. The
latter imply an incorrect concept of the problem
and indicate an error on the part of the person
developing the mathematical model. Implementation
errors, on the other hand, refer to errors encoun-
tered when encoding an error free algorithm into a
directed graph. A directed graph is composed of
many types of nodes, each of which has specific
functions and specific rules of usage. As a system
becomes larger or more complex, it becomes increas-
ingly difficult for the designer to visualize the
!ystem in its entirety and it becomes, therefore,
This research was supported in part by the Advanced
Research Projects Agency of the Department of De-
fense through contract SD-302 and by the Division
of Research Facilities and Resources of the National
Institutes of Health through grant FR-002l8.
29
increasingly probable that some node's rule of
usage will be violated. If a system is designed
or reconfigured according to a graph containing an
implementation error, the system will malfunction.
This is not a desirable way of detecting errors,
however, since the amount of time spent in locating
and correcting the source or sources of malfunction
may be greater than the time advantage to be gained
from the restructuring. If, therefore, a highly-
restructurable system is to be used to fullest
advantage, debugging time must be minimized and, if
possible, made automatic.
The problem of automatic detection of imple-
mentation errors is the authors' area of interest
and the topic of this paper. The approach presented
is to represent the directed graph as an arc-node
connection matrix and then by a systematic reduction
procedure, attempt to reduce the matrix down to a
single cell. If this is possible, the graph was
error free; if not, an error exists at that step
in the procedure where further reduction is impos-
sible.
Control Elements
When considering concurrent processing, tech-
niques for the manipulation of data remain essen-
tially the same as in standard ;;;q;:;entlal processing,
with perhaps the need for some type of Interlock to
mediate conflicting concurrent requests for data,
as from memory. Discussion of these considerations
can be found in Bernstein's work. (5)
In considering control operations, however, the
need arises for new types of control devices, for
the elementary control transfers of sequential
programming are not sufficient to accomodate the
wider variety of operations encountered in con-
current operations. In constructing asynchronous
systems utilization of distributed control instead
of the conventional centralized control is advan-
tageous. This distributed control must be manipu-
lated, or changed, and this is performed by means
of "control elements". The general control element
is depicted in Figure 1 in which :. I and E
Figure 1. Generalized Control Element
are sets of incident and extant control lines and
; D is a set of data. Thus a typical output line
Ei ~an be described as a function of the incident
control and the incident data, that is,
£: = " - ' '.' ' Al though numerous con trol
devices are conceivable, we shall define but four
for use in the present analysis. These four meta
control elements are the branch, rendezvous, deci-
sion, and merge. These are denoted by B, R, D and
M respectively as shown in Figure 2. The branch
for when a NO decision is made, the recursive path,
PQS will be stopped at the rendezvous element
permanently -- and the program will not function
properly. This then is an implementation error.
Certainly the detection and correction of such
errors is quite simple in such an elementary con-
figuration; two possible solutions are shown in
Figures 4 and 5; but, in more complex algorithms
this detection becomes exceptionally difficult and
automatic error detection schemes most certainly
are warran ted.
Figure 2. Meta Control Elements
produces two simultaneous extant control signals
which are independent of incident data. Thus the
branch allows the initiation of parallel operations.
The rendezvous element (whose operation is also
independent of data) terminates concurrent sequences
by yielding an output only after both incident
signals have been received. The decision element
produces an output on only one of the extant lines,
the particular line being dictated by the value of
the incident data. The merge element produces an
output for a signal on either of its incident lines;
its operation is not defined if its input signals
are not mutually exclusive. Similar control func-
tions (such as DO TOGETHER, WAIT, FORK, JOIN, etc.)
have been described in the literature pertaining
to higher level languages for multiprocessing (6)
but we are referring here to actual hardware devices
rather than program statements. To illustrate both
the use of these elements and also to show how
implementation errors may easily intrude into a
program, consider the computer statements:
Analysis of Control Systems
The problem of analyzing a design in which
decision-making and parallel processing are highly
interdependent has several solutions, such as ex-
haustive testing, simulation, logical equation
manipulation and list processing. However, a graph
theoretic viewpoint, in which manipulative tech-
niques on an arc-node connection matrix are used,
is emphasized in this paper. A method for parti-
tioning a graph into classes of compatible nodes is
developed in which a class of compatible nodes is
defined as subgraph haVing only one incident and
extant arc to the class, and all other arcs attached
to nodes in the class are either incident or extant
to nodes within the class.
Using the partitioning technique and several
theorems relating to simple configurations of nodes,
this technique can reduce practically all realistic
designs to a few small complex subgraphs. At this
point in the analysis two alternatives are postu-
lated. First, these complex subgraphs could merely
be presented to the user for verification. Second,
these subgraphs could be subjected to detailed
automatic analysis techniques. (Which are too
time-consuming if the entire flow-graph is analyzed.)
To illustrate how these techniques are applied to
more complex algorithms several examples are
presented in this paper. The control structure
for one of these, a floating point arithmetic
unit, is pictured in Figure 6.
In this paper we have introduced a new degree
of freedom available to the computer user-pro-
grammer when employing a restructurable computer
for implementation of concurrent processing. Dis-
cussion of errors arising in this context have
been analyzed and several error detecting schemes
presented. The arc-node method with prior node
partitioning appears to be the most realistic
approach at this time. In the future we believe
that increasing importance will be placed on these
aspects of error detecting and the systhesis of
concurrent processing algorithms. However, even
until more sophisticated solutions are found, many
important and useful systems may be constructed
using the elements and methods we have discussed.
Conclusions
Statement
Transfer contents of register B to reg. C
Complement contents of register A
Add one to contents of register A
If A : 0 then go to EXIT else go to
Exit
Statement
Number
This may be represented in abbreviated form as:
B -. C
COMP A
INDX A
A : O?, 1, EXIT
One implementation of this algorithm in a concurrent
flow-graph is shown in Figure 3. Observe that this
implementation of the algorithm contains an error,
1.
2.
3.
References
Ornstein, S.M., Stucki, M.J., and Clark, W.A.,
"A Functional Description of Macromodules",
Proc. S.J.C.C., pp. 337-355, 1967.
Stucki, M.J., Ornstein, S.M., and Clark, W.A.,
"Logical Design of Macromodules", Pr oc , S.J.C.C.,
pp. 357-364, 1967.
Clark, W.A., Stucki, M.J., and Ornstein, S.M.,
lOA Macromodular Approach to Computer Design",
Technical Report #1, February, 1966, Computer
30
~F--
f;:,
Figure 5. Correct Implementation - Case B
Research Laboratory, Washington University,
St. Louis, Missouri.
4. Estrin, G., "Organization of Computer Systems:
The Fixed Plus Variable Structure Computer",
Pr oc , W.J.C.C., pp , 33-40, 1960.
5. Bernstein, A.J., "Analysis of Programs for
Parallel Processing", IEEE Transactions on
Electrical Computers, Vol. EC-15, pp. 757-764,
October, 1966.
6. Dennis, J.B., and Van Horn, E.C., "Programming
Semantics for Multiprogrammed Computations",
Comm. of the ACM, Vol. 9, pp. 143-155,
March, 1966.
Figure 3. Incorrect,Implementation of Algorithm
.--------1 B)i------
Figure 4. Correct Implementation - Case A
31
Figure 6.
32
Entry 2


Problems Encountered With Control Networks in Highly-Restructurable Digital Systems

Scholarship@Claremont

Claremont CollegesScholarship @ ClaremontAll HMC Faculty Publications and Research HMC Faculty Scholarship9-1-1967Problems Encountered With Control Networks inHighly-Restructurable Digital SystemsDonald F. WannRobert A. EllisMishell J. StuckiRobert M. KellerHarvey Mudd CollegeThis Article is brought to you for free and open access by the HMC Faculty Scholarship at Scholarship @ Claremont. It has been accepted for inclusionin All HMC Faculty Publications and Research by an authorized administrator of Scholarship @ Claremont. For more information, please contactscholarship@cuc.claremont.edu.Recommended CitationWann, D.F., R.A. Ellis, M.J. Stucki, and R.M. Keller. "Problems encountered with control networks in highly-restructurable digitalsystems." Digest of the First Annual IEEE Computer Conference (September 1967): 29-32.D.F. WannPROBLEMS ENCOUNTERED WITH CONTROL NETWORKSIN HIGHLY RESTRUCTURABLE DIGITAL SYSTEMSR.A. Ell is M.J. StuckiWashington UniversitySt. Louis, MissouriR.M. KellerABSTRACT. This paper discusses problems encountered with control networks in highly restructurabledigital systems. In particular the treatment of implementation errors is covered with emphasis on con-current processing. The implementation of concurrent processing networks may result in errors which willbe quite complex to detect and systematic methods are warranted. Four meta control elements are employedin obtaining convenient concurrent structures. We analyze several error detecting schemes and concludethat the arc-node method with node partitioning appears to be the most realistic approach at this time.IntroductionIn this paper we discuss aspects of concurrentcontrol structures encountered in the context ofthe Macromodular Project being carried out at Wash-ington University. (1) (2) Although many of theideas to be presented apply specifically to macro-modular systems, we feel that these systems are thefirst of a new class of highly-restructurable sys-tems, (3)(4) and that the considerations to be dis-cussed are characteristics of this class.Macromodules are digital building blocks thatare rather unique in that data processing struc-tures constructed from them are isomorphic to adirected graph and can, therefore, be designed andanalyzed from a graph-theoretic viewpoint. Thenodes of the graph correspond to the macromodulesthemselves and the arcs of the graph correspond tothe control cables that interconnect the modules.All electrical and mechanical considerations havebeen eliminated by careful design of the units,and the design of data processing structures istherefore an exercise in logic only.The macromodular concept makes possible dataprocessing avenues not possible in fixed structuredsystems. Specifically, the ease with which macro-modular structures may be re-configured and aug-mented makes it possible for a system user to altera system's configuration so as to be more efficientfor his particular problem area. There are manyways in which the efficiency of a system may beaffected: machine instructions may be changed tobetter fit the problem area, machine instructionsmay be re-designed in a highly parallel or con-current fashion to minimize the operating time ofthe system, etc .• As is to be expected, however,opportunities such as these are not without accom-panying pitfalls. It has been discovered that inthe process of formatting a system alteration andimplementing it into the system it is extremelyeasy to make what we shall call "implementationerrors" as contrasted to algorithm errors. Thelatter imply an incorrect concept of the problemand indicate an error on the part of the persondeveloping the mathematical model. Implementationerrors, on the other hand, refer to errors encoun-tered when encoding an error free algorithm into adirected graph. A directed graph is composed ofmany types of nodes, each of which has specificfunctions and specific rules of usage. As a systembecomes larger or more complex, it becomes increas-ingly difficult for the designer to visualize the!ystem in its entirety and it becomes, therefore,This research was supported in part by the AdvancedResearch Projects Agency of the Department of De-fense through contract SD-302 and by the Divisionof Research Facilities and Resources of the NationalInstitutes of Health through grant FR-002l8.29increasingly probable that some node's rule ofusage will be violated. If a system is designedor reconfigured according to a graph containing animplementation error, the system will malfunction.This is not a desirable way of detecting errors,however, since the amount of time spent in locatingand correcting the source or sources of malfunctionmay be greater than the time advantage to be gainedfrom the restructuring. If, therefore, a highly-restructurable system is to be used to fullestadvantage, debugging time must be minimized and, ifpossible, made automatic.The problem of automatic detection of imple-mentation errors is the authors' area of interestand the topic of this paper. The approach presentedis to represent the directed graph as an arc-nodeconnection matrix and then by a systematic reductionprocedure, attempt to reduce the matrix down to asingle cell. If this is possible, the graph waserror free; if not, an error exists at that stepin the procedure where further reduction is impos-sible.Control ElementsWhen considering concurrent processing, tech-niques for the manipulation of data remain essen-tially the same as in standard ;;;q;:;entlal processing,with perhaps the need for some type of Interlock tomediate conflicting concurrent requests for data,as from memory. Discussion of these considerationscan be found in Bernstein's work. (5)In considering control operations, however, theneed arises for new types of control devices, forthe elementary control transfers of sequentialprogramming are not sufficient to accomodate thewider variety of operations encountered in con-current operations. In constructing asynchronoussystems utilization of distributed control insteadof the conventional centralized control is advan-tageous. This distributed control must be manipu-lated, or changed, and this is performed by meansof "control elements". The general control elementis depicted in Figure 1 in which :. I and EFigure 1. Generalized Control Elementare sets of incident and extant control lines and; D is a set of data. Thus a typical output lineEi ~an be described as a function of the incidentcontrol and the incident data, that is,£: = " - ' '.' ' Al though numerous con troldevices are conceivable, we shall define but fourfor use in the present analysis. These four metacontrol elements are the branch, rendezvous, deci-sion, and merge. These are denoted by B, R, D andM respectively as shown in Figure 2. The branchfor when a NO decision is made, the recursive path,PQS will be stopped at the rendezvous elementpermanently -- and the program will not functionproperly. This then is an implementation error.Certainly the detection and correction of sucherrors is quite simple in such an elementary con-figuration; two possible solutions are shown inFigures 4 and 5; but, in more complex algorithmsthis detection becomes exceptionally difficult andautomatic error detection schemes most certainlyare warran ted.Figure 2. Meta Control Elementsproduces two simultaneous extant control signalswhich are independent of incident data. Thus thebranch allows the initiation of parallel operations.The rendezvous element (whose operation is alsoindependent of data) terminates concurrent sequencesby yielding an output only after both incidentsignals have been received. The decision elementproduces an output on only one of the extant lines,the particular line being dictated by the value ofthe incident data. The merge element produces anoutput for a signal on either of its incident lines;its operation is not defined if its input signalsare not mutually exclusive. Similar control func-tions (such as DO TOGETHER, WAIT, FORK, JOIN, etc.)have been described in the literature pertainingto higher level languages for multiprocessing (6)but we are referring here to actual hardware devicesrather than program statements. To illustrate boththe use of these elements and also to show howimplementation errors may easily intrude into aprogram, consider the computer statements:Analysis of Control SystemsThe problem of analyzing a design in whichdecision-making and parallel processing are highlyinterdependent has several solutions, such as ex-haustive testing, simulation, logical equationmanipulation and list processing. However, a graphtheoretic viewpoint, in which manipulative tech-niques on an arc-node connection matrix are used,is emphasized in this paper. A method for parti-tioning a graph into classes of compatible nodes isdeveloped in which a class of compatible nodes isdefined as subgraph haVing only one incident andextant arc to the class, and all other arcs attachedto nodes in the class are either incident or extantto nodes within the class.Using the partitioning technique and severaltheorems relating to simple configurations of nodes,this technique can reduce practically all realisticdesigns to a few small complex subgraphs. At thispoint in the analysis two alternatives are postu-lated. First, these complex subgraphs could merelybe presented to the user for verification. Second,these subgraphs could be subjected to detailedautomatic analysis techniques. (Which are tootime-consuming if the entire flow-graph is analyzed.)To illustrate how these techniques are applied tomore complex algorithms several examples arepresented in this paper. The control structurefor one of these, a floating point arithmeticunit, is pictured in Figure 6.In this paper we have introduced a new degreeof freedom available to the computer user-pro-grammer when employing a restructurable computerfor implementation of concurrent processing. Dis-cussion of errors arising in this context havebeen analyzed and several error detecting schemespresented. The arc-node method with prior nodepartitioning appears to be the most realisticapproach at this time. In the future we believethat increasing importance will be placed on theseaspects of error detecting and the systhesis ofconcurrent processing algorithms. However, evenuntil more sophisticated solutions are found, manyimportant and useful systems may be constructedusing the elements and methods we have discussed.ConclusionsStatementTransfer contents of register B to reg. CComplement contents of register AAdd one to contents of register AIf A : 0 then go to EXIT else go toExitStatementNumberThis may be represented in abbreviated form as:B -. CCOMP AINDX AA : O?, 1, EXITOne implementation of this algorithm in a concurrentflow-graph is shown in Figure 3. Observe that thisimplementation of the algorithm contains an error,1.2.3.ReferencesOrnstein, S.M., Stucki, M.J., and Clark, W.A.,"A Functional Description of Macromodules",Proc. S.J.C.C., pp. 337-355, 1967.Stucki, M.J., Ornstein, S.M., and Clark, W.A.,"Logical Design of Macromodules", Pr oc , S.J.C.C.,pp. 357-364, 1967.Clark, W.A., Stucki, M.J., and Ornstein, S.M.,lOA Macromodular Approach to Computer Design",Technical Report #1, February, 1966, Computer30~F--f;:,Figure 5. Correct Implementation - Case BResearch Laboratory, Washington University,St. Louis, Missouri.4. Estrin, G., "Organization of Computer Systems:The Fixed Plus Variable Structure Computer",Pr oc , W.J.C.C., pp , 33-40, 1960.5. Bernstein, A.J., "Analysis of Programs forParallel Processing", IEEE Transactions onElectrical Computers, Vol. EC-15, pp. 757-764,October, 1966.6. Dennis, J.B., and Van Horn, E.C., "ProgrammingSemantics for Multiprogrammed Computations",Comm. of the ACM, Vol. 9, pp. 143-155,March, 1966.Figure 3. Incorrect,Implementation of Algorithm.--------1 B)i------Figure 4. Correct Implementation - Case A31Figure 6.32Entry 2

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Problems Encountered With Control Networks in Highly-Restructurable Digital Systems

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