Amarnath, Aporva

Beaumont, Jonathan

Blaauw, David

Chakrabarti, Chaitali

Cole, Murray

Dreslinski, Ronald

Feng, Siying

He, Xin

Kaszyk, Kuba

Kim, Hun-Seok

Kim, Sung

May, Kyle

Morton, John Magnus

Mudge, Trevor

O'Boyle, Michael

Pal, Subhankar

Park, Dong-hyeon

Sun, Jiawen

Xiong, Yan

Yang, Chi-Sheng

English

With the end of Dennard scaling and Moore’s law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularly true for domains that have frequently changing algorithms and applications involving mixed sparse/dense data structures, such as those in machine learning and graph analytics. To overcome this, we present a flexible accelerator called Transmuter, in a novel effort to bridge the gap between General-Purpose Processors (GPPs) and Application-Specific Integrated Circuits (ASICs). Transmuter adapts to changing kernel characteristics, such as data reuse and control divergence, through the ability to reconfigure the on-chip memory type, resource sharing and dataflow at run-time within a short latency. This is facilitated by a fabric of light-weight cores connected to a network of reconfigurable caches and crossbars. Transmuter addresses a rapidly growing set of algorithms exhibiting dynamic data movement patterns, irregularity, and sparsity, while delivering GPU-like efficiencies for traditional dense applications. Finally, in order to support programmability and ease-of-adoption, we prototype a software stack composed of low-level runtime routines, and a high-level language library called TransPy, that cater to expert programmers and end-users, respectively.Our evaluations with Transmuter demonstrate average throughput (energy-efficiency) improvements of 5.0× (18.4×) and 4.2× (4.0×) over a high-end CPU and GPU, respectively, across a diverse set of kernels predominant in graph analytics, scientific computing and machine learning. Transmuter achieves energy-efficiency gains averaging 3.4× and 2.0× over prior FPGA and CGRA implementations of the same kernels, while remaining on average within 9.3× of state-of-the-art ASICs

Edinburgh Research Explorer

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

Abadi Martin

Adelson Edward H

Ayhan Tuba

Buck Ian

Chang Web

Cuturi Marco

Jr E Swartzlander Earl

Halfhill Tom R

Ipek Engin

Jackson Preston A.

Suleman M. Aater

Komuravelli Rakesh

Kusner Matt J.

Logan Beth

Nowatzki Tony

Ovtcharov Kalin

Pal Subhankar

Schuiki Fabian

Steffl Samuel

Yamazaki Ichitaro

Crossref

Transmuter

https://www.research.ed.ac.uk/portal/files/164483167/Transmuter_PAL_DOA24072020_AFV.pdf

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

Abstract

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