odel checking, which allows the designer to check that certain desired properties hold of the system. However, the normal 1 a b s 0 b c s 1 a c s 2 s 0 s 1 s 0 s 1 s 2 s 2 s 1 s 0 Figure 1: A CTL structure and corresponding computation tree requirement that specifications be expressed in temporal logic has proved an obstacle to its adoption by circuit designers---hence the motivation for a natural language interface. 2.2 Computation Tree Logic The SMV program implements a model checking algorithm where circuit properties are expressed in the temporal logic CTL [CES86]. In models of CTL, the temporal order < defines a tree which branches towards the future. CTL formulas that start with A express necessity. AG f is true at a time<F
