Grant, L. A.

Henderson, Robert

English

Edinburgh Research Explorer

     Edinburgh Research Explorer                                      Reduction of Band-to-band Tunneling in Deep-submicron CMOSSingle Photon Avalanche PhotodiodesCitation for published version:Henderson, R & Grant, LA 2009, 'Reduction of Band-to-band Tunneling in Deep-submicron CMOS SinglePhoton Avalanche Photodiodes'. in International Image Sensor Workshop.Link:Link to publication record in Edinburgh Research ExplorerDocument Version:Author final version (often known as postprint)Published In:International Image Sensor WorkshopGeneral rightsCopyright for the publications made accessible via the Edinburgh Research Explorer is retained by the author(s)and / or other copyright owners and it is a condition of accessing these publications that users recognise andabide by the legal requirements associated with these rights.Take down policyThe University of Edinburgh has made every reasonable effort to ensure that Edinburgh Research Explorercontent complies with UK legislation. If you believe that the public display of this file breaches copyright pleasecontact openaccess@ed.ac.uk providing details, and we will remove access to the work immediately andinvestigate your claim.Download date: 20. Feb. 2015Reduction of Band-to-band Tunneling in Deep-submicron CMOS Single Photon Avalanche Photodiodes Robert K. Henderson[1], Justin Richardson[1,2], Lindsay Grant[2] [1]The University of Edinburgh, Institute for Integrated Micro and Nano Systems, Edinburgh, U.K,  Robert.Henderson@ed.ac.uk, Tel: +44 131 650 5568 [2]STMicroelectronics Imaging Division, Edinburgh, UK. Justin.Richardson@st.com. Lindsay.Grant@st.com, Tel: + 44 131 336 6000  SUMMARY We demonstrate that a process layer intended for pinned-photodiode formation can be employed to reduce the dark count rate (DCR) of single photon avalanche diodes (SPADs) in nanometer-era CMOS technologies. A low-doped p-type passivation implant reduces the electric field in the p-diffusion/nwell breakdown region and acts both as a guard ring and as an STI edge interface. An 8µm diameter device with a typical DCR of 40Hz at 25C is reported in a 130nm CMOS imaging process. I. INTRODUCTION Single-photon avalanche diodes operating in Geiger mode are highly promising solid-state replacements for photomultiplier tubes (PMTs) in scientific or biomedical imaging [1,2]. Integration of these detectors in CMOS technology is a relatively recent innovation with the first detectors reported in 0.8µm CMOS, progressing rapidly in recent years to deep-submicron processes [3,4].  A number of CMOS SPADs have been proposed recently at 180nm or 130nm process nodes [5,6,7,8,9]. However, the authors consistently report excessive noise levels induced by band-to-band tunneling in the high field region of the device. Suitable field profiles for the SPAD avalanche region cannot easily be obtained due to the increased doping levels of source/drain p-diffusion and n-well in scaled CMOS process technologies. Thus, trends for PMOS transistor formation are now contrary to the requirements for SPAD detectors. Yet nanometer-era digital processing is an enabling technology for future single-photon imagers, promising picosecond time-to-digital conversion and large, low-power, time-resolved pixel arrays in a small form-factor. In this paper we demonstrate that a single process implant found in CMOS image sensor technology can be employed to reduce the dark count noise in p-diffusion/n-well SPAD structures by several orders of magnitude. The detector can be fabricated without additional mask steps or doping level modifications.  II. DEEP SUBMICRON CMOS SPAD DEVICE STRUCTURES A number of SPAD structures have been proposed in deep-submicron CMOS in recent years (Figures 2a-e) [3,4,5,6,7,8,9]. A SPAD with low DCR and high photon detection efficiency (PDE) requires the engineering of (1) a suitable guard ring to prevent premature breakdown at the device periphery and (2) a uniform, high field, breakdown region. While a number of guard ring designs have been proposed, the breakdown region is consistently formed by the p-n junction between p+ diffusion source-drain implant and n-well.  At 0.8µm and 0.35µm process nodes, SPADs with implicit guard rings, formed by either an enrichment n-well implant or by n-well spacing, were successful at providing low DCR [1,3,4]. Beyond the 250nm node, the introduction of STI and triple-well process steps has required new SPAD structures and we focus mainly on these modern process generations in this paper.         (a)         (b) Fig. 1 180nm CMOS SPAD structures (a) [7] (b) [8]  The most common approach is to create an explicit guard ring of low doped p-well material around the central p+/n-well breakdown region. Two SPADs with such a structure have been reported at the 180nm process node [7,8] with the former at around 100Hz DCR and the latter  at around 100kHz. Both authors cite band-to-band tunneling effects as being present. Yet another SPAD at 180nm [9], proposes the use of STI as the guard region but with even higher DCR of 1MHz thought to be due to traps at the STI-interface. At the 130nm process node, various devices employing a p-well guard ring have been reported, invariably with high DCR (40-100kHz). Passivation of STI-interface traps has failed to reduce DCR significantly leading to the assumption that tunneling is the dominant mechanism.  This is evidenced by  DCR temperature dependence, and confirmed by TCAD modelling showing that the high field in the narrow p+/nwell depletion region is giving rise to excessive band-to-band tunneling [10]. Unfortunately, this is a trend that is set to continue, as doping levels are being increased in nanometer-era CMOS to maintain transistor performance. STISTISTISTIn+ n+n-well n-welldeep n-well (retrograde)p-subn-wellp+p-well p-wellSTISTIn+ n+n-well n-welldeep n-well (retrograde)p-subn-wellp+p-well p-wellSTISTI         (a)          (b)  Fig. 2 SPAD structures (a) STI guard ring [9] (b) pwell guard ring with STI passivation [6] III. NEW SPAD DEVICE STRUCTURE It is clear from the previous discussion that the p+/nwell breakdown region must be modified to reduce the field strength. There are various possible approaches (1) change the doping profile by process modification (2) choose entirely different, lower-doped p or n layers (3) modify the doping profile of the existing p+/nwell junction by an additional implant. Approaches (1) and (2) have been shown to be successful in forthcoming publications [10][11]. In this work, we demonstrate that strategy (3) can also be applied.           Fig. 3 Enrichment SPAD in triple-well CMOS technology  The SPAD structure proposed in this paper is an adaptation of an enrichment SPAD structure [1][4] shown in Fig. 3 to a triple-well technology.  The guard ring is formed implicitly, by the absence of p-well, creating a ring of p-epi doped with the graded (retrograde) doping profile of the buried n-well. The p-well formation can be prevented by a drawn ring of implant stop layer.  The high field at the interface between n-well and p+ diffusion will favour breakdown in this planar region without, however, solving the band-to-band tunneling problem. The cross-section of the new device structure is shown in Fig. 4 and a micrograph is shown in Fig. 5. The cathode terminal is formed by a deep retrograde n-well with the n-well enrichment implant defining the active breakdown region. The deep n-well is contacted at the periphery of the device by a ring of n-well with n-diffusion contacts.            Fig. 4  New SPAD structure (this work)    Fig. 5 SPAD Micrograph showing dummy fill elements  The anode terminal is formed by the conjunction of a conventional p-diffusion ring surrounded by a deeper, low-doped p-type implant. This p- implant is available in the CMOS imaging process where it fulfils the role of a glove-like passivation implant around the STI to reduce dark current in pinned-photodiodes, as employed originally in Fig. 2b [6]. The combination of the two p-type implants forms a less abrupt, graded junction which greatly reduces tunneling dark count compared to the conventional p+/n-well junction. The p- implant also acts as a guard ring structure. Whereas conventional guard rings are formed by a ring of lower doped p-well, we prevent p-well formation by a drawn implant stop layer. Instead, the lower field region is formed in the ring where the p- implant extends beyond n-well. This region is also where the p-epi wafer material is implanted with retrograde deep n-well. The p- implant makes a natural interface to the STI edge without the intermediary of a polysilicon thin oxide ring as in [5]. STI-bounded SPADs are highly attractive for dense integration with electronics [9].  IV. RESULTS Fig. 6 shows the IV curve of the device. The breakdown voltage is around 12.4V indicating a lower field in the avalanche region when compared to 9.6V breakdown of p-diffusion/n-well SPADs [5,6,7,8]. The current at breakdown is 124.6pA. STISTISTISTIn+ n+p-subn-wellp+STISTISTISTIn+ n+n-well n-welldeep n-well (retrograde)p-subp+n-wellp-STISTIn+ n+n-well n-welldeep n-well (retrograde)p-subn-wellp+p-well p-wellSTISTISTISTISTISTIn+ n+n-well n-welldeep n-well (retrograde)p-subn-wellp+p-epi/deepn-wellp-epi/deepn-well Fig. 6 SPAD I-V curve  Fig. 7 (a) Dark count versus excess bias voltage (VEB) (b) Dark count versus temperature  Fig. 7a shows the variation of DCR with excess bias voltage. The variation of DCR with temperature in Fig. 7b shows an increased slope above 20C which is indicative of thermal generation. Below that temperature the DCR doubles every 30C indicating the onset of band-to-band tunneling. Fig. 8 illustrates the PDE variation with wavelength exhibiting a peak of around 20% at 450nm increasing with excess bias voltage. The PDE is improved by the reduced stack height of the imaging process. Finally, a plot of device jitter is given in Fig. 9 showing the absence of a significant tail and an FWHM of around 200ps. A 470nm, 80ps jitter pulsed laser diode has been employed in measurements. V. CONCLUSIONS Use of the extended palette of layers intended for pinned-photodiode formation in CMOS imaging processes has been effective at reducing dark count of a p+/nwell SPAD structure. Furthermore, we believe that a low noise device, dispensing with the p- ring and relying solely on the STI boundary will be possible since the tunnelling-induced DCR has been addressed by the p+/p-/n-well graded junction. REFERENCES [1] Cova S.,Ghioni M., Zappa F., Rech I., Gulinatti, A., “A view on progress of silicon single photon avalanche diodes,” Adv. Photon Counting Tech. Proc. SPIE, vol. 6372, p. 63720I-1, Oct. 2006. [2] Jackson, J., et al., “Toward integrated single-photon-counting microarrays,” Opt. Eng., vol. 42, no. 1, pp. 112–118, Jan. 2003. [3] Rochas A., et al., “First fully integrated 2-D array of single-photon detectors in standard CMOS technology,” IEEE Photon. Technol. Lett., vol. 15, no. 7, pp. 963–965, Jul. 2003. [4] Pancheri, L., Stoppa, D.: ‘Low-Noise CMOS Single-Photon Avalanche Diodes with 32ns Dead Time’, 37th ESSDERC, pp362-365 2007. [5] Niclass, C., Gersbach, M., Henderson, R.K., Grant, L., Charbon, E.: ‘A Single Photon Avalanche Diode Implemented in 130nm CMOS Technology’, Selected Topics in Quantum Electronics, IEEE Journal of, Vol. 13, No. 4, 2007, p863-869. [6] Gersbach, M, Niclass, C., Charbon, E., Richardson, J., Henderson, R., Grant, L., "A single photon detector implemented in a 130nm CMOS imaging process," Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European , vol., no., pp.270-273, 15-19 Sept. 2008. [7] Faramarzpour, N., Deen, M.J., Shirani. S., Fang, Q.: ‘Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18um Technology’, Electron Devices, IEEE Transactions on, Vol. 55, Issue 3, 2008, p760-767. [8] Marwick, M.A., Andreou, A.G.:‘Single photon avalanche photodetector with integrated quenching fabricated in TSMC 0.18µm 1.8V CMOS process’, Electronics Letters, Vol. 44, No. 10, 2008,  p643-644. [9] Finkelstein, H., Hsu, M.J., Esener, S.C.: ‘STI-Bounded Single Photon Avalanche Diode in a Deep-Submicrometer CMOS Technology’, IEEE Electron Device Letters, Vol. 27, Issue 11, 2006, p887-889. [10] Gersbach M., Richardson J., Mazaleyrat E., Hardillier S., Niclass C., Henderson R., Grant L., Charbon E., “A Low-Noise Single Photon Detector Implemented in a 130nm CMOS Imaging Process”, J. Solid-State Electronics, in press. [11] Richardson J., Grant L., Henderson R., “A Low Dark Count Single Photon Avalanche Diode Structure Compatible with Standard Nanometer Scale CMOS Technology”, International Image Sensor Workshop, 2009.                    VEB=0.2V  VEB=0.6V  VEB=1.0V Fig. 8 Photon detection efficiency versus wavelength at various excess bias voltages  VEB=0.2V  VEB=0.6V  VEB=1.0V Fig. 9 Jitter at various excess bias voltage with illumination from a pulsed 470nm laser diode 

A Low Dark Count Single Photon Avalanche

A LowNoise Single Photon Detector Implemented in a 130nm CMOS Imaging Process”, J. Solid-State Electronics,

A single photon detector implemented in a 130nm CMOS imaging process,&quot;

A view on progress of silicon single photon avalanche diodes,” Adv. Photon Counting Tech.

Andreou, A.G.:‘Single photon avalanche photodetector with integrated quenching fabricated

E.: ‘A Single Photon Avalanche Diode Implemented in 130nm CMOS Technology’, Selected Topics in Quantum Electronics,

First fully integrated 2-D array of single-photon detectors in standard

Q.: ‘Fully Integrated Single Photon Avalanche Diode Detector

S.C.: ‘STI-Bounded Single Photon Avalanche Diode in a Deep-Submicrometer CMOS Technology’,

Toward integrated single-photoncounting microarrays,”

Reduction of Band-to-band Tunneling in Deep-submicron CMOS Single Photon Avalanche Photodiodes

Reduction of Band-to-band Tunneling in Deep-submicron CMOS Single Photon Avalanche Photodiodes

Abstract

Similar works

Full text

Available Versions

Edinburgh Research Explorer