In recent years, Support Vector Machine (SVM) classifiers have played a crucial role in providing data fusion and high accuracy classification solutions for various, complex, non-linear problems. Their popularity accompanied by the ever-increasing need of implementing it on computationally weak, portable or even wearable systems has refueled the effort to accelerate their execution. In this paper, we explore FPGA-based acceleration to produce efficient SVM hardware co-processors. We propose a systematic two-level approach for SVM acceleration, which first optimizes the global structure of the original SVM’s behavioral description to exploit the data- and instruction-level parallelism and then further refines it through a targeted design exploration that matches the accelerator’s memory architecture to its computation and memory access patterns. The proposed methodology has been implemented as a framework on top of Vivado High-Level Synthesis (HLS) tool. We evaluate the effectiveness of the methodology through a rich set of analysis and validation results, which show that its adoption delivers SVM accelerator designs achieving latency gains of up to 98.78 % in respect to Vivado-HLS default optimized solution. Finally, using as a case study an ECG analysis and Arrhythmia detection system we show that a target Zynq programmable SoC utilizing the optimized SVM accelerator design outperforms pure software implementations in numerous single or dual core target platforms, achieving speedups, which range from 10 × up to 78 ×
