Becker, Jürgen

Bähr, Steffen

Iwasaki, Yoshihito

Kim, KyungTae

Lai, Yun-Tsung

Unger, Kai Lukas

English

KITopen

PoS(TWEPP2019)145Realization of a state machine based detection forTrack Segments in the Trigger System of the Belle IIExperiment∗Kai Lukas Unger†Karlsruhe Institute of Technology (KIT)E-mail: kai.unger@kit.eduSteffen BährKarlsruhe Institute of Technology (KIT)Jürgen BeckerKarlsruhe Institute of Technology (KIT)Yoshihito IwasakiHigh Energy Accelerator Research Organization (KEK)KyungTae KimKorea University (KU)Yun-Tsung LaiHigh Energy Accelerator Research Organization (KEK)The Belle II experiment relies on an online level 1 trigger system to reduce the background andachieve the targeted frequency of 30 kHz. Here the basis for all trigger decisions based on datafrom the Central Drift Camber is the track segment finding. To improve both efficiency andmaintainability we restructured the original combinatorial approach to finite state machines. Thenew implementation is saving about 20% of FPGA slices. To achieve high test coverage anautomated test framework was developed for design time validation. Operational correctness isachieved by integration in cosmic ray tests.Topical Workshop on Electronics for Particle Physics TWEPP20192-6 September 2019Santiago de Compostela - Spain∗Sponsored by the German Federal Ministry of Education and Research†Speaker.c© Copyright owned by the author(s) under the terms of the Creative CommonsAttribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0). https://pos.sissa.it/PoS(TWEPP2019)145State Machine TSF in Belle II CDC Kai Lukas Unger1. IntroductionThe Belle II experiment aims at detecting B mesons decays caused by collisions of electrons(7 GeV) with positrons (4 GeV). A record luminosity of L = 8 ∗ 10(35)cm−2s−1 is expected [1].The event rate reaches 130 kHz which is too high to record all the data. Therefore, the triggersystem reduces the event rate to 30 kHz and ensures that only relevant data will be stored [5]. TheCentral Drift Chamber (CDC) is the main detector for track reconstruction. The L1 trigger chain ofthe CDC can be seen in Figure 1. The basis of all processing are represented by the Track SegmentFinder (TSF). Afterwards the reduced data is passed on to the 2D Finder and the 3D Finder, whichestimate the track parameters from the data. Furthermore, the Event Time Finder gets the collisiontime and the Z-Vertex Track Trigger [3] receive the information to estimate the origin and angleof the collision. All this informations are gathered in the Global Decision Logic, which evaluateswhether the data is relevant or not [4].CDCReadout2DFinderEvent TimeFinder3D Finderz-VertexTrackTriggerGlobal Decision LogicTrackSegmentFinderFigure 1: Overview over the L1 Trigger Chain for the Central Drift Chamber1.1 Track Segment FindingThe TSF identifies Track Segments in the data of the CDC. To achieve this, five layers ofwires are combined to a Super Layer and compared with predefined geometric shapes, called tracksegments. In Super Layer 0 the track segments are organized in a pyramid-like shape. Tracksegments in Super Layer 1 to 8 have houerglass-like shape. This arrangement is shown in Figure 2and intended limit the possible origin angle to around 30◦ of the collision origin.rϕL R1L R1Super Layer 0 Super Layer 1-8Figure 2: Shape of the Track Segments (red).The dark green line is the First Priority andthe brighter green is the Second PriorityFirst Prioritypassage leftSecond Prioritypassage rightSecond Prioritypassage unknownFigure 3: Possible Track Passage in SuperLayer 1-8 (red). The arrow shows the detecteddirectionIn each track segment, there are three special cells. Each cell represents a priority status, eitherfirst or secondary left/right L/R priority. All first priority cells across one Super Layer are assignedwith a unique ID that is used to identify one specific segment. The Track Segment ID contains thenumber of the First Priority and the Super Layer. If there is only a Second Priority Hit, in total fourlayers with hits in a time window of ∼ 500ns are required for an output. In addition the L/R solutionand the hitposition are added to the output as well. The intention behind the L/R solution is shown1PoS(TWEPP2019)145State Machine TSF in Belle II CDC Kai Lukas Ungerin Figure 3. It gives the passage of a particle to either the left, right or an unknown direction. Thispassage is calculated using a predefined lookup table, since online computation is too complex andexceeds the available latency budget. This lookup table is implemented using the FPGA’s BRAM.2. Concept2.1 State MachinewaitsecondfirstCounter 0Counter 0First Priority Hit/Track Segment OutputFirst Priority Hit/Track Segment OutputSecond Priority Hit/Track Segment OutputFigure 4: States and conditions of the TSFState machine345678918192021222324253536373839404150515253545556576768697071727356721223853546970714562021375253686970First Priority Hit Second Priority HitFigure 5: Possible Track Passage and thetwo associated output Track SegmentsThe State Machine is implemented as a Mealy machine. Figure 4 gives an overview of itsstates in which events in CDC data are detected. The FSM starts in the "wait" state. After a FirstPriority Hit occurs, the output of the Track Segment is send and the state transitions to the nextstate "first", where a conter lasting for ∼ 500ns started for the FSM. During this time, any newhits are suppressed. This delay is required for the ionized gas returning to its resting state. Anyadditional hit within this time window is assumed to belong to the same track. When the counterget to zero, the state changes back to "wait" and the logic back to observation of the CDC. If thereis a Second Priority Hit the state changes to "second" and set the counter for ∼ 500ns. If during thisperiod a First Priority Hit occurs, the FSM transitions from a Second Priorty Hit ("second" ) to aFirst Priority Hit ("fist" ), which works as described above. If this happens, the new Track Segmentoutputed out and the counter is new set to ∼ 500ns.2.2 Neighbor Hit SuppressionSince only 15 Track Segments can be transmitted to the following Trigger Systems once each31.75 MHz clock cycle, it is important to avoid redundant information. The Neighbor Hit Suppres-sion algorithm allows a data reduction by not transmitting Second Priority hits when a First PriorityHit has occurred in a neighboring Track Segment.Figure 5 shows a possible double output of a First Prioriy Hit and a Second Priority Hit resultingfrom the same particle track. In the particle trajectory shown in the example, the Second PriorityHit from cell 37 generates an additional output to the First Priority Hit from cell 38. The NeighborHit Suppression algorithm suppressed any Second Priority Hit from a neighboring cell for ∼ 125nstime. Only the First Priority Hit will be transmitted. The Neighbor Hit Suppression algorithm isimplemented as a State Machine with two distinct states ("no_neighbor_hit" and "neighbor_hit" ),where the "no_neigbor_hit" is the initial state. If a first priority hit in a neighbor Track Segmentoccurs, the state changes from "no_neighbor_hit" to "neighbor_hit" and a counter of 125ns is set,2PoS(TWEPP2019)145State Machine TSF in Belle II CDC Kai Lukas Ungercounting down to zero. While there is no Second Priority Hit allowed within the 125ns window, ifther is a First Priority Hit, it will generate a First Priority output. When the counter is zero the statechanges back to the initial state "no_neighbor_hit".2.3 Dual Port BRAM useThe Xilinx Virtex 6 FPGA used in the experiment has Dual Ports Block RAMS (BRAMS). Thesecond read port can also be used to resolve the L/R result determination, as it is a read-only lookuptable. The problem here, is that for each Super Layer the L/R result determination is the same. Inthe case where faulty wire is present within a Track Segment a new lookup table has to be used. Towork around this problem, a configuration has been introduced that assigns the appropriate BRAMto each track segment. By using Dual Port feature, the BRAM resource consumption is reduced,and the bad wire does not impact the L/R ambiguity decision.3. Evaluation3.1 FPGA ResourcesThe state machine implementation in the Universal Trigger Board 3’s Xilinx XC6VHX565TFPGA is integral to the Belle II experiment. The highest resource consumption of the Xilinx comesfrom the most outer Super Layer, layer 8, because it processes more data than the inner SuperLayers, with a 24 ∗ 256 bit parallel input every 31.75ns. Table 1 shows the resource consumptionof the old implementation compared to the new state machine version. The use of Slice Registersand LUTs is reduced by 20% over all Super Layers. The lookup tables and flip-flops (LUT-FF) areabout 30% reduced over all Super Layers. The bigger LUT-FF reduced at Super Layer 8 are comingfrom special adjustment for this Super Layer. By using both ports of the dual port, the occupancyof the BRAMs B36E1 has decreased. The BRAM resource usage to determine the L/R ambiguityis reduced by 50%. The overall reducetion is less than 50% because some BRAMs are used inother Parts of the TSF. This reduction is important for the final integration, as BRAM buffers arelimited.Table 1: Super Layer 8 resource usage from the old implementation and the new state machine of the XilinxXC6VHX565T FPGASlice Register Slice LUTs LUT-FF BRamold Implementation 295116 223432 163883 430state machine 214788 174714 69198 2523.2 ValidationThe implementation was validated across all Super Layers in simulation and integrated in theexperiment’s trigger system. The integrated system is validated with both cosmics and collisions. Inall cases, it shows the expected behavior achieving high efficiency in finding both First and SecondPriority Hits. According to initial preliminary analyses, the efficiency is close to the theoreticalpotential of the system. Analyses that are more precise are still in progress.3PoS(TWEPP2019)145State Machine TSF in Belle II CDC Kai Lukas Unger4. SummaryThe upgraded SuperKEKB collider is designed to achieve a luminosity of L = 8∗10(35)cm−2s−1.As a result higher machine background is expected in the attached Belle II experiment comparedto its predecessor Belle. The estimated event rates exceed the targeted trigger rate of 30 kHz. Oneof the major trigger systems employed to achieve this rate is the trigger system of the central driftchamber at the Level 1. Here the basis for all present trigger algorithms is the Track SegmentFinder. Its task is to detect regions of active wires in the detector and combine them into tracksegments, arrangements of neighboring wires that conform to a predefined geometrical shape. Thetrack segment finder is implemented on XC6VHX565T Virtex 6 FPGAs and integrated close to thedetector readout. It has to be efficient and operate in low latency to fullfill the requirements of theentire Level 1 trigger system. A combinatorial approach was in operation for the first phases of theexperiment. To increase efficiency and maintainability we present a restructured implementationbased on finite state machines. The advantages of the new state machine implementation are theeasier expandability as well as the lower resource consumption. By reducing resources, we are ableto ease the achievement of timing closure for further iterations of the firmware. Additionally weadded a mechanism to reduce transmission of redundant data and thus improve operation by em-ploying suppression of neighboring hits. The overall design is reworked to provide a higher degreeof flexibility during design time. We incorporated an approach to adjust track segment finding forpredefined regions of the central drift chamber by allowing partial loading of special track findingconfigurations. This will allow easy adjustment for geometrical regions with broken wires. As thisfinding mechanism is based on BRAM, we developed an automated dual and single port inferenceto keep resource consumption to a minimum. On average the new implementation is capable ofachieving a reduction of used Slice LUTs of about 20%. To validate the new implementation, wedeveloped a test framework to support target high test coverage or dedicated detector data patternsto investigate special cases. The trigger system is validated using cosmic rays.References[1] Z. Dolez̆al and S. Uno, Bell II Collaboration "Belle II Technical Design Report" KEK Report 2010,October 2010. Available: https://arxiv.org/abs/1011.0352[2] N. Taniguchi et al. "All-in-one readout electronics for the Belle-II Central Drift Chamber" :doi.org/10.1016/j.nima.2013.06.096[3] S. Baehr et al. "A neural network on FPGAs for the z-vertex track trigger in Belle II" 2017. Journal ofInstrumentation, 12, Art. Nr.: C03065. doi:10.1088/1748-0221/12/03/C03065[4] Y. Iwasaki et al., "Level 1 Trigger System for the Belle II Experiment," in IEEE Transactions onNuclear Science, vol. 58, no. 4, pp. 1807-1815, Aug. 2011. doi: 10.1109/TNS.2011.2119329[5] E. Kou et al.. The Belle II Physics Book. 2018. (hal-01902963)4

Realization of a state machine based detection for Track Segments in the Trigger System of the Belle II Experiment

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Realization of a state machine based detection for Track Segments in the Trigger System of the Belle II Experiment

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