High dielectric constant tantalum-pentoxide insulating layers were prepared on p-type (100) crystalline silicon wafers using an RF magnetron sputtering technique. Then, metal-oxide-semiconductor (Al-Ta 2O 5-Si) structures were formed with various oxide thickness from 15 to 25 nm. Devices were characterized using the high frequency capacitance-voltage (C-V) spectroscopy method. From the analysis of the high frequency C-V curves, non-ideal effects such as oxide charges and interface trap densities have been evaluated. The results for Ta 2O 5 layers have been compared with those for conventional SiO 2 layers. Interface trap densities were found to be 1.6 ± 0.4×10 12 eV -1 cm -2 for Ta 2O 5 and about 2×10 11 eV -1 cm -2 for SiO 2 insulating layers. There was no clear thickness dependence of the interface trap densities for the Ta 2O 5 insulating layers

Atanassova, Elena

Güneş, Mehmet

Özdağ, Pınar

English

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The	effects	of	oxide	thickness	on	the	interface
and	oxide	properties	of	metal-tantalum
pentoxide-Si	(MOS)	capacitors
Article		in		Journal	of	Optoelectronics	and	Advanced	Materials	·	February	2005
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Journal of Optoelectronics and Advanced Materials Vol. 7, No.  1, February 2005, p. 293 - 296 
 
 
 
 
 
 
THE EFFECTS OF OXIDE THICKNESS ON THE INTERFACE AND OXIDE 
PROPERTIES OF METAL-TANTALUM PENTOXIDE-SI (MOS) CAPACITORS 
 
 
P. Ozdag, E. Atanassovaa, M.Gunes* 
 
Department of Physics, Izmir Institute of Technology, Izmir, Turkey  
                   aInstitute of Solid State Physics, Bulgarian Academy of Sciences, Sofia, Bulgaria 
 
 
High dielectric constant tantalum-pentoxide insulating layers were prepared on p-type (100) 
crystalline silicon wafers using an RF magnetron sputtering technique. Then, metal-oxide-
semiconductor (Al-Ta2O5-Si) structures were formed with various oxide thickness from 15 
to 25 nm. Devices were characterized using the high frequency capacitance-voltage (C-V) 
spectroscopy method. From the analysis of the high frequency C-V curves, non-ideal effects 
such as oxide charges and interface trap densities have been evaluated. The results for Ta2O5 
layers have been compared with those for conventional SiO2 layers. Interface trap densities 
were found to be 1.6 ± 0.4×1012 eV-1 cm-2 for Ta2O5 and about 2×1011 eV-1 cm-2 for SiO2 
insulating layers. There was no clear thickness dependence of the interface trap densities for 
the Ta2O5 insulating layers. 
  
(Received December 9, 2004; accepted January 26, 2005) 
 
Keywords: Metal-oxide-semiconductor (MOS) capacitors, Tantalum pentoxide,  
                  Capacitance-voltage spectroscopy 
  
 
1. Introduction 
 
High dielectric constant insulating layers have become important to replace the native 
silicon dioxide used for the gate dielectric of DRAMS [1, 2 and references therein]. The search for a 
replacement for SiO2 not only requires a high dielectric constant but also chemical stability with Si, 
a low leakage current and wide band gap properties. Among all the candidates, Ta2O5 layers have 
received considerable attention because of their potential application as dielectric films for storage 
capacitors in high density DRAMs [3-6] due to the relatively high dielectric constant (20-40), high 
refractive index and adequate dielectric breakdown strength [7 and references therein, 8]. It has also 
been demonstrated that the dielectric constant of Ta2O5 layers shows a thickness dependence [7-10]. 
Nevertheless, there are a number of problems that have to be overcome before sufficient reliability 
can be provided in modern integrated circuit fabrication. One of them is the defect density in the 
structure of the Si-Ta2O5 interface and that in the oxide. In general, these defect states in the SiO2 
system are characterized qualitatively, using high frequency capacitance-voltage measurements and 
quantitatively by using the conductance spectroscopies [11]. However, in high dielectric constant 
insulators, the investigation of these defect states is rather difficult, due to high leakage currents 
through the oxide. In the present paper, the effects of the oxide thickness on the interface properties 
of Si-Ta2O5 structure are investigated using the high frequency C-V characteristics of Al-Ta2O5-
Si(p) (MOS) structures and the effective oxide charges and interface trap densities are obtained 
using Terman’s method [12]. 
                                         
*
 Corresponding author: mehmetgunes@iyte.edu.tr 
P. Ozdag, E. Atanasssova, M. Gunes  
 
 
294 
 2. Experimental procedure 
 
Tantalum pentoxide films with thicknesses of 15 – 25 nm were deposited on p-type (100), 
15 Ω cm Si, by RF magnetron sputtering from a tantalum target in an Ar atmosphere. The system 
base pressure was 6×10-4 Pa, the working gas pressure 3 Pa, the RF power density 2.2 W/cm2, the 
deposition rate, ν = 9.3 nm/min, and the substrate temperature Ts = 300K. After the deposition, the 
Ta films were oxidized in dry oxygen at atmospheric pressure at 873 K with an O2 flow rate of  
5.1 min-1. It is proposed that the oxidation temperature, Tox, is low enough for oxidation of the 
silicon substrate to be negligible, and the formation of tantalum silicide is prevented. The thickness 
tox of the Ta2O5 layers was measured by ellipsometry (λ = 632.8 nm) and layers with tox = 15, 20  
and 25 nm were investigated. For the electrical characterization, MOS capacitors were fabricated by 
evaporation of Al dots with a thickness of 500 nm, through a shadow mask with a gate electrode 
area of 1.96×10-3 cm2. Post metallization annealing was carried out in H2 at 723 K for 1h. High 
frequency C-V measurements were carried out using a Keithley Model 82 system, and the data were 
acquired by a computer through an IEEE-488 interface bus. The dielectric constant, doping 
concentration and flat band voltage values were determined from the experimental high frequency 
C-V curves. Theoretical ideal C-V characteristics were calculated using a computer program and 
equations defined for MOS devices [13,14]. The effective oxide charge density ,Neff, and the density 
of interface defect states, Dit, were calculated from the high frequency C-V curves using Terman’s 
method [12,14].  
  
 
3. Results and discussion 
  
The experimental high frequency C-V characteristics of Al-Ta2O5-Si(p) (MOS) capacitors 
with different oxide thicknesses are shown in Fig. 1. These curves represent the typical high 
frequency C-V dependence of a MOS capacitor. The doping concentrations of the devices are almost 
identical (2×1015 cm-3), as obtained from the 1/C2 vs. VG curves. The flat-band voltages, VFB, due to 
non-ideal effects present in MOS capacitors, were found to be -1.74, -1.77 and -1.63 V for oxide 
thicknesses of 15, 20 and 25 nm, respectively. The effect of the oxide thickness is clearly reflected in 
the magnitude of the oxide capacitance dominating in the accumulation region, since the areas of the 
devices are equal and the dielectric constant did not change significantly at these oxide thicknesses. 
The parameters derived from the high frequency C-V measurements are also summarized in Table 1, 
where the dielectric constant, εοx, of Ta2O5 is 11.7 ± 0.9, in agreement with recent reports [7-10]. In 
addition, the experimental high frequency C-V curves of an Al-SiO2-Si MOS capacitor prepared on 
a p-type Si wafer with a 1.17×1015 cm-3 doping concentration is shown in Fig. 1, to compare the 
effect of the dielectric constant of Ta2O5 layers on the oxide capacitance. For the same 20 nm oxide 
thickness and gate area, the oxide capacitance of the Al-SiO2-Si(p) MOS capacitor shifts to lower 
values due to the different  dielectric constant. 
VG (V)
-10 -8 -6 -4 -2 0 2
C 
(nF
)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
tox= 15 nm
tox= 20 nm
tox= 20 nm (SiO2)
tox= 25 nm
 
Fig. 1. High frequency (1MHz) capacitance-voltage characteristics of Al-Ta2O5-Si (MOS) 
capacitors  with  different  oxide  thicknesses,  and  that of conventional Al-SiO2-Si capacitor  
                                             with an oxide thickness of 20 nm. 
The effects of oxide thickness on the interface and oxide properties of … 
 
 
295
Table 1. Summary of  the parameters extracted from the high frequency C-V measurements. 
Data presented here are the average of several device characteristics measured from different  
                                                          parts of the substrate wafer  
 
tox (nm)Sample εox Cox (pF) Na (cm
-3)
x1015 VFB (volt)
Neff (cm-2)
x1012
Ta2O5
15
20
25
20SiO2
10.1
12.6
11.8
1165
1093
818
250
2.04
1.95
2.15
1.17
-1.74
-1.77
-1.63
-1.31
3.11
3.02
1.90
0.343.9
 
 
 
The theoretical capacitance versus surface potential, ψs, was calculated using the 
corresponding theoretical equations defined for MOS capacitors [13,14] and the extracted 
experimental values of the doping concentration, NA, oxide thickness, dielectric constant and gate 
area. Both the experimental and theoretical (ideal) normalized capacitance (C/Cox) versus gate 
voltage data are plotted together in Fig. 2, for insulating layers of Ta2O5 and SiO2. It is clearly seen 
that the experimental normalized C-V curve shifts from the ideal one, due to non-ideal effects 
present in the MOS devices. The flat-band voltage, VFB, values obtained for each sample are also 
indicated on the normalized capacitance curves. Using these voltage shifts, the effective oxide 
charge density, Qeff, and effective number of charges per unit area, Neff, are calculated using equation 
(10.10) of reference [14]. These are also summarized in Table 1. For oxide layers of thickness 15 
and 20 nm, Neff is about 3.1×1012 cm-2 and decreases to 1.90×1012 cm-2 for a 25 nm thick Ta2O5 
layer. The level of Neff found here is in the same order as reported for the other metal oxide layers 
proposed for the replacement of SiO2 [1]. However, Neff is 3.4×1011 cm-2, approximately ten times 
lower than for native oxide SiO2, in agreement with reported results [1].  
-10 -8 -6 -4 -2 0 2
C/
Co
x
0.0
0.2
0.4
0.6
0.8
1.0
VG (V)
-8 -6 -4 -2 0 2
VG (V)
VFB
Ta2O5 , t=25 nm SiO2 , t=20 nm
VFB
Experimental
Theoretical
Experimental
Theoretical
(a) (b)
 
 Fig. 2. Normalized experimental and theoretical capacitance-voltage curves of MOS  
                  capacitors with an insulating layer of (a) Ta2O5 and ( b) SiO2. 
 
 
In addition, the shifts between the theoretical and experimental curves are not only due to 
oxide charges but also to states at the oxide-Si interface. Using the theoretical and experimental 
normalized capacitance curves, the surface potential ψs versus gate voltage VG curve was obtained 
for each sample, and the density of interface trap states, Dit, was calculated using Terman’s method 
[12]. The distribution of Dit values obtained for the Ta2O5 and SiO2 insulating layers is shown in Fig. 
3, as a function of the energy in the bandgap of the silicon. The value of Dit for Ta2O5 is  
1.6±0.4 × 1012 cm-2 eV-1, and does not show a clear dependence on the oxide thickness. 
 
 
 
× × 
P. Ozdag, E. Atanasssova, M. Gunes  
 
 
296 
Ev Et (eV)
0.0 0.1 0.2 0.3 0.4 0.5 0.6
D
it 
(cm
 
-
2  
e
V 
-
1 ) 
x 
10
 
12
0
2
4
6
tox= 15 nm
tox= 20 nm
tox= 25 nm
midgap
tox= 20 nm (SiO2)
 
Fig. 3. Density of interface trap states as a function of energy in the bandgap of c-silicon for  
                                               Ta2O5 and SiO2 insulating layers.  
 
 However, these values are much higher than that of native oxide SiO2, and are above the limit 
for the requirement of Dit (< 2×1011 cm-3 eV-1), as specified by a detailed investigation [1] of the 
possibilities for the replacement of the gate dielectric in technological applications, for  device 
dimensions of less than 50 nm. 
 
 
 4. Conclusions 
  
 The use of of Ta2O5 insulating layers, less than 30 nm thick, in MOS capacitors was 
examined in terms of the oxide and Si-oxide interface properties, which were investigated using high 
frequency C-V spectroscopy. They were compared with those of native SiO2 insulating layers. It was 
found that Ta2O5 layers contain almost ten times higher concentrations of effective oxide charges 
than native oxide SiO2. The density of traps at the Si-Ta2O5 interface is about  
1.6 ±0.4×1012 cm-2 eV-1, and does not show a systematic dependence on the oxide thickness. The 
values of Dit are still much higher than that of the SiO2-Si interface and above the limit for the 
requirement of Dit (< 2×1011 cm-3 eV-1) as specified by a detailed investigation [1] of the possibilities 
for the replacement of the gate dielectric in technological applications, for  device dimensions of less 
than 50 nm. 
 
 
 References 
 
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  [2] C. Chaneliere, J. L. Autran, R. A. B. Devine, B. Balland, Materials Science and Engineering 
         R22, 269 (1998). 
  [3] P. Singer, Semicond. International 4, 56 (1994). 
  [4] H. Shrinki, M. Nakata, IEEE Trans. Electron. Devices ED-38, 455 (1991). 
  [5] R. Devine, Appl. Phys. Lett. 68, 1924 (1996). 
  [6] H. Shinriki, T. Kisu, S. L. Kimura, Y. Nishioka, Y. Kawamoto, K. Mukai, IEEE Trans. El. Dev.  
        37, 1939 (1990).  
  [7] T. Dimitrova, E. Atanassova, Solid-State Electronics 42, 307 (1998). 
  [8] S. Ezhilvalavan, T. Y. Tseng, Journal of Materials Science: Materials in Elect. 10, 9 (1999). 
  [9] A. Paskaleva, E. Atassova, T. Dimitrova, Vacuum 58, 470 (2000). 
[10] E. Atanassova, Microelectronics Reliability 39, 1185 (1999). 
[11] E. H. Nicollian, A. Goetzberger, A. D. Lopez, Solid State Electronics 12, 937 (1969). 
[12] L. M. Terman, Solid- State Electron 5, 285 (1962). 
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The effects of oxide thickness on the interface and oxide properties of metal-tantalum pentoxide-Si (MOS) capacitors

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The effects of oxide thickness on the interface and oxide properties of metal-tantalum pentoxide-Si (MOS) capacitors

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